The Architecture and Development Flow of the S5 Software Configurable Processor

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

High-rate Complex Orthogonal Space-time Block Codes for 5 and 6 Transmit Antennas

Based on orthogonal designs, space-time (ST) block codes that enable full diversity as well as a simple maximum likelihood (ML) decoding algorithm at the decoder can be constructed for more than two transmit antennas. For real constellations (such as PAM), ST block codes with transmission rate 1 can be designed from the real Hurwitz-Radon families for any number of transmit antennas. However, for complex constellations (such as M-PSK or M-QAM), ST block codes for more than two transmit antennas can only be constructed with rates less than 1. Previous attempts have been concentrated on complex orthogonal designs that provide ST block codes with full diversity and high transmission rates. In this paper, we present two rate 2/3 complex ST block codes from orthogonal designs for five and six transmit antennas, respectively. Simulation results are provided to demonstrate the significant performance gains made by the proposed ST block codes.

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

This paper discusses an automated method to divide scan chains into multiple scan segments that are suitable for power-constrained at-speed testing using the skewed-load test application strategy. By dividing a circuit into multiple partitions, which can be tested independently, both power during shift and power during capture can be controlled. Despite activating one partition at a time, we show how through conscious construction of scan segments, high transition fault coverage can be achieved, while reducing test time of the circuit and employing third party test generation tools.

Adaptive Bit Loading and Transmit Diversity for Iterative OFDM Receivers

In this paper, we consider a transmission system employing orthogonal frequency division multiplexing with bit-interleaved coded modulation and perfect channel state information at both transmitter and receiver. An adaptive bit loading scheme in combination with cyclic delay diversity and discontinuous Doppler diversity is proposed at the transmitter and iterative demapping and decoding at the receiver. The loading procedure minimizes the bit-error rate at the decoder output, and the transmit diversity schemes mitigate channel correlations. We analyze the iterative receiver with extrinsic information transfer charts and present the achievable gains.

ASIP Approach for Implementation of H.264/AVC

This paper presents an Application Specific Instruction Set Processor (ASIP) for implementation of H.264/AVC, called Video Specific Instruction-set Processor (VSIP). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has coprocessors for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The proposed VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. Moreover, the proposed hardware accelerators have small size, consume low power consumption, and thus, they can support real-time video processing. VSIP has been thoroughly verified using an FPGA board having the Xilinx™ Virtex II. VSIP can implement a real-time H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.

Role of Convergence in GIMCV Development: A Vision

Path to Global Information Multimedia Communication Village (GIMCV) can be seen as a convergence process among telephony, data exchange and television. Convergence refers not only to various services provided by the same operator but also by the same device, the same access network, the same transport network, etc. This paper present authors’ vision on how convergence will lead the GIMCV development.

Priority-driven Coding and Transmission of Progressive JPEG Images for Real-Time Applications

Since high-quality image/video systems based on the JPEG/MPEG compression standards often require power-expensive implementations at relatively high bit-rates, they have not been widely used in low-power wireless applications. To alleviate this problem, we designed, implemented, and evaluated a strategy that can adapt to different compression and transmission rates. (1) It gives important parts of an image higher priority over unimportant parts. Therefore, the high-priority parts can achieve high image quality, while the low-priority parts, with a slight sacrifice of quality, can achieve huge compression rate and thus save the power/energy of a low-power wireless system. (2) We also introduce a priority-driven scheduling approach into our coding algorithm, which makes the transmission of important parts earlier with more data than other parts. Through a balanced trade-off between the available time/bandwidth/power and the image quality, this adaptive strategy can satisfy users with desired images quality and lead to a significant reduction of the important parts’ deadline misses.

A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at .

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MGFs for Rayleigh Random Variables

Expressions are given for the moment generating functions of the Rayleigh and generalized Rayleigh distributions.

Fixed point analysis of limited range share per node wavelength conversion in asynchronous optical packet switching systems

In this article, we study an asynchronous optical packet switch equipped with a number of wavelength converters shared per node. The wavelength converters can be full range or circular-type limited range. We use the algorithmic methods devised for Markov chains of block-tridiagonal type in addition to fixed-point iterations to approximately solve this relatively complex system. In our approach, we also take into account the finite number of fiber interfaces using the Engset traffic model rather than the usual Poisson traffic modeling. The proposed analytical method provides an accurate approximation for full range systems for relatively large number of interfaces and for circular-type limited range wavelength conversion systems for which the tuning range is relatively narrow.

RF Testing on a Mixed Signal Tester

In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test plan developed includes fast, cost-effective and dedicated circuitry.

Reconfigurable Component-based Middleware for Networked Embedded Systems

Next generation embedded systems will be composed of large numbers of heterogeneous devices. These will typically be resource-constrained (such as sensor motes), will use different operating systems, and will be connected through different types of network interfaces. Additionally, they may be mobile and/or form ad-hoc networks with their peers, and will need to be adaptive to changing conditions based on context-awareness. Our focus in this paper is on the provision of a middleware framework for such system environments. Our approach is based on a small and efficient ‘middleware kernel’ which supports highly modularised and customisable component-based middleware services that can be tailored for specific embedded environments, and are runtime reconfigurable to support adaptivity. These services are primarily communications-related but also address a range of other concerns including service discovery and logical mobility. In the paper we provide an overview of our approach, focusing in detail on both the middleware kernel and the services. We also discuss an application scenario in which we are currently applying and evaluating our middleware approach.

A Survey of Cryptographic Primitives and Implementations for Hardware-Constrained Sensor Network Nodes

In a wireless sensor network environment, a sensor node is extremely constrained in terms of hardware due to factors such as maximizing lifetime and minimizing physical size and overall cost. Nevertheless, these nodes must be able to run cryptographic operations based on primitives such as hash functions, symmetric encryption and public key cryptography in order to allow the creation of secure services. Our objective in this paper is to survey how the existing research-based and commercial-based sensor nodes are suitable for this purpose, analyzing how the hardware can influence the provision of the primitives and how software implementations tackles the task of implementing instances of those primitives. As a result, it will be possible to evaluate the influence of provision of security in the protocols and applications/scenarios where sensors can be used.

Performance Verification of Successive Interference Cancellation for STBC MIMO-OFDM System with Channel Correlation

Multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) transmission can improve both the transmission capacity and performance due to diversity gain. However, when the antennas are close to each other in a MIMO-OFDM system, the diversity order will be decreased because of channel correlation. In the paper performance of various detection methods for space–time block code (STBC) MIMO-OFDM with channel correlation are evaluated, including the conventional Alamouti full matrix detection, the modified diagonal matrix detection, the least square-zero forcing (LS-ZF) detection, and the successive interference cancellation (SIC). The paper also verify that the SIC detection can still keep excellent detection performance under large channel correlation.

A New Routing Metric for Satisfying Both Energy and Delay Constraints in Wireless Sensor Networks

Besides energy constraint, wireless sensor networks should also be able to provide bounded communication delay when they are used to support real-time applications. In this paper, a new routing metric is proposed. It takes into account both energy and delay constraints. It can be used in AODV. By mathematical analysis and simulations, we have shown the efficiency of this new routing metric.

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency.

An Expression for the Average Quantization Error

The quantization error for MIMO (multiple-input multiple-output) downlink channels is known to be the minimum of independent and identically distributed beta random variables. In this note, an exact expression is derived for the average quantization error. Computational issues relating to its correctness, usage and approximations are discussed.

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function

High-speed and low area hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-up Table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An unrolled Whirlpool architecture implemented on the Virtex XC4VLX100 device achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures. A low area iterative architecture, which utilises 64-bit operations as opposed to full 512-bit operations, is also described. It runs at 430 Mbps and occupies 709 slices on a Virtex X4VLX15. This proves to be one of the smallest 512-bit hash function architectures currently available.

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over \mathbbF2163 \mathbb{F}_{{2^{{163}} }} using Gaussian Normal Bases

This paper presents a comprehensive analysis of the design of custom instructions in a reconfigurable hardware platform dedicated to accelerate arithmetic operations in the binary field , using a Gaussian normal basis representation. The resulting platform is capable of running real applications, thus allowing a precise measurement of the execution overheads, and a fair comparison of the hardware and software speedups at several implementation levels. By using this approach, we determine which field operations (e.g., multiplication) are better suited to constrained environments, and which ones provide an enhanced performance in general-purpose systems. Experimental results reveal that by using our fastest field multiplier implemented as a custom instruction in a combined hardware/software approach, we accelerate point multiplication (the fundamental operation in Elliptic Curve Cryptography) over 126 times.