An Algorithm for Adaptive Mean Filtering and Its Hardware Implementation

Noise due to the sensor and the electronics of a camera is an undesirable issue in any machine vision application. Such noise tends to corrupt images and to obstruct any further analysis. An algorithm to detect and cancel such noise, using statistical methods, is presented in this paper. The proposed algorithm is an adaptive mean filter, which filters out image regions that are found to be noise corrupted. The efficiency of the proposed filter was examined both qualitatively and quantitatively, by software simulation in several noisy conditions. The main advantage of the filter in hand is that it is appropriate for hardware implementation and can be easily incorporated to smart cameras. The hardware implementation of the filter is also presented in this paper. This implementation aims at time critical applications such as machine vision, inspection and visual surveillance. Ioannis Gasteratos holds a Diploma in Electrical Engineering from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, 2004. His research interests include digital VLSI design, computer architectures and artificial intelligence. He is a member of the IEEE, and a member of the Technical Chamber of Greece (TEE). Antonios Gasteratos is a Lecturer of Robotics in the Department of Production and Management, Democritus University of Thrace, Greece. He holds a PhD from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, 1999. During 2001–2003 he was a visiting Assistant Professor in the Department of Electrical and Computer Engineering, Democritus Univesrsity of Thrace. He serves as a reviewer to numerous of Scientific Journals and International Conferences. His research interests are mainly in computer and robot vision and sensory data fusion. He is a member of the IEEE, the IAPR, the EURASIP, the Hellenic Society of Artificial Intelligence (SETN) and the Technical Chamber of Greece (TEE). Ioannis Andreadis received the Diploma Degree from the Department of Electrical & Computer Engineering, DUTH, Greece, in 1983 and the MSc and PhD Degrees from the University of Manchester Institute of Science & Technology, UK, in 1985 and 1989, respectively. His research interests are mainly in Intelligent Systems, Machine Vision and VLSI based computing architectures. He joined the Department of Electrical & Computer Engineering, DUTH in 1993. He is a member of the Editorial Board of the Pattern Recognition Journal, TEE and IEEE.     

A 10-Bit,Low Power,Successive Approximation,Digitally Auto-Zeroed CMOS ADC Core for the NASA TRIO Smart Sensor System on a Chip

In spacecraft applications there is a great need for robust analogue to digital converters (ADC) that can withstand the harsh space environment. Commercially available ADCs cannot operate in the space environment due to radiation effects. In this paper we present an ADC that has been developed for the NASA TRIO smart sensor system on a chip (SoC), a versatile low power device specifically designed for spacecraft data acquisition and telemetry of several types of sensors such as temperature, voltage/current transducers, radFETs, etc. It is required for the ADC to operate in excess of 300 Krad total ionizing dose and to be robust to single event upsets. The successive approximation topology was chosen and it was enhanced with a special auto-zeroing technique to compensate for possible lifetime offset errors. Due to the comparator design, a rail-to-rail input capability is achieved, a feature very useful in some type of Vdd ratio metric sensors. It has 10-bit resolution for a reference in the range 0.1 to Vdd + 1 V, and for power supply in the range 2.5 to 5.5 V; the positive reference terminal V_ref+ is settable up to Vdd + 0.5 V and the negative voltage terminal is settable down to GND-0.5 V. The power dissipation is less than 2 mW at 50 Ksamlles/sec. The TRIO chip is used in several NASA spacecraft including CONTOUR, STEREO, MESSENGER, EUROPA, PLUTO, etc.George Kottaras was born in Athens, Greece in 1974. He received the Diploma degree (five years with thesis) in Electrical Engineering from Democritos University of Thrace, Greece in 1996. He is currently pursuing the Ph.D. degree on Scientific Space Instruments and spacecraft avionics at Space Research Laboratory, DUTh. He has specialized in VLSI technologies at JHU/APL for about five years.His research interests include mixed signal analog/digital design, ADCs, design for testability, testing, smart sensors and data acquisition.Nikolaos P. Paschalidis was born is Serres, Greece in 1963. He received the Diploma and Ph.D. degrees in Electrical Engineering from the Democritus University of Thrace (DUTh), Greece, in 1985 and 1992 respectively. He has been in appointment with the Johns Hopkins University, since 1989, where his research specialized in advanced microelectronics, space instrumentation, and space physics.He later joined the Space Department of JHU Applied Physics Laboratory (JHU/APL) Laurel, MD, as a postdoctoral fellow and presently he is Principal Staff. His research interests are in analog and mixed signal microelectronics, microsensors, microsystems and their applications in in-situ and remote sensing spacecraft instruments and avionics. He pioneered in the Advanced Technology Development program of NASA for smaller better faster missions by leading efforts in the circuit level of: amplifiers, comparators, voltage references, ADC and DAC, PLLs, TDCs, SEU and radiation tolerant design, physical design, design for testability, testing and space qualification; in the system on a chip level flight ready chips including: the Time of Flight chip for precise time pickoff and time digitization, Energy chip for radiation energy measurement, the TRIO smart sensor chip for spacecraft data acquisition and control etc; in the instrument and spacecraft level: application of these technologies in particle and plasma spectrometers, laser altimeters, photon/particle imagers, TOF mass spectrometers, X-ray and gamma-ray instruments, spacecraft avionics. Space missions using these technologies include: Cassini, Image, Contour, Messenger, Pluto, Mars missions, etc. Dr. Paschalidis published extensively in microelectronics, space instrumentation, and space physics. He supervises research of graduate students in ECE and Applied Physics. He supervised DUTh graduate students at JHU/APL for many years. He participates as principal investigator and co-investigator in several space programs; he participates in communities with space related activities including: the IEEE Aerospace, Nuclear Sciences, NASA VLSI, IAA, and American Geophysical Union.Emmanuel T. Sarris was bom in Athens, Greece, in 1945. He received the physics degree from the University of Athens in 1967 and the Ph.D. degree in space physics from the University of Iowa, Iowa City, in 1973.He was a Postdoctoral Fellow in the Applied Physics Laboratory, The Johns Hopkins University, Baltimore, MD, from 1974 to 1976. From 1976 to 1977, he was a Research Scientist at the Max-Planck-Institut. He has been a Professor of Electrodynamics, Department of Electrical Engineering, University of Thrace, Greece, and Director of the Laboratory of Electrodynamics and Space Research since 1977. He was the Director of the Institute of Ionospheric and Space Physics, National Observatory of Athens from 1990 to 1996. His research interests include space plasma electrodynamics, design, construction, and testing of space instrumentation, satellite communications, satellite remote sensing. He is coinvestigator in the international space missions: Ulysses, Geotail, Interball, Cluster. He is the author of 270 refereed publications and 300 presentations at international meetings. Dr. Sarris is a member of the COSPAR Council. He was elected Johns Hopkins Scholar Award in 1992 and received the Award for Academic Excellence in 1994.Nikos Stamatopoulos was born in Peloponnisos, Greece in 1969. He received the diploma degree (five years with thesis) of Electrical Engineering from Democritos University of Thrace, Greece in 1994. He is currently pursuing the Ph.D. degree on Scientific Space Instruments at Space Research Laboratory, DUTh. He has specialized in VLSI technologies with emphasis in low noise analog design at JHU/APL for about five years.His main research interests are on Analogue CMOS VLSI design for fast time acquisition.Kostas Karadamoglou was born in Macedonia, Greece, in 1970. He received the diploma degree (five years with thesis) of Electrical Engineering from Democritos University of Thrace, Greece in 1994. He is currently pursuing the Ph.D. degree on Scientific Space Instruments at Space Research Laboratory, DUTh. He has specialized in VLSI technologies with emphasis in high-speed digital design at JHU/APL for about five years.His main research interests are on the design of application specific Time to Digital Converters.Vassilis Paschalidis was born in Serres, Greece in 1964. He received the B.S. degree in Electrical Engineering from the Technological Institute of Kabala, Greece in 1988. He worked n the industry for electronic automation. He has specialized in VLSI technologies at JHU/APL for about five years with emphasis in physical design. His research interests include mixed signal analog/digital VLSI design.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Capacity and Error Probability for Maximal Ratio Combining Reception over Correlated Nakagami Fading Channels

In this paper, the capacity and error probability of maximal ratio combining (MRC) reception are considered for different modulation schemes over correlated Nakagami fading channels. Based on an equivalent scalar additive white Gaussian noise (AWGN) channel, we derive the characteristic function (CF) and the probability density function (PDF) of the signal to noise ratio for MRC reception over Nakagami fading channels. Using these CF and PDF results, closed form error probability and capacity expressions are obtained for PSK, PAM and QAM modulation. Wei Li received his Ph.D. degree in Electrical and Computer Engineering from the University of Victoria in 2004. He is now a Post-doctoral Research Fellow in the Department of Electrical and Computer Engineering at the University of Victoria. He is a Member of the IEEE. His research interests include ultra-wideband system, spread spectrum communications, diversity for wireless communications, and cellular communication systems. Hao Zhang was born in Jiangsu, China, in 1975. He received his Bachelor Degree in Telecom Engineering and Industrial Management from Shanghai Jiaotong University, China in 1994, his MBA from New York Institute of Technology, USA in 2001, and his Ph.D. in Electrical and Computer Engineering from the University of Victoria, Canada in 2004. His research interests include ultra-wideband radio systems, MIMO wireless systems, and spectrum communications. From 1994 to 1997, he was the Assistant President of ICO(China) Global Communication Company. He was the Founder and CEO of Beijing Parco Co., Ltd. from 1998 to 2000. In 2000, he joined Microsoft Canada as a Software Engineer, and was Chief Engineer at Dream Access Information Technology, Canada from 2001 to 2002. He is currently an Adjunct Assistant Professor in the Department of Electrical and Computer Engineering at the University of Victoria. T. Aaron Gulliver received the Ph.D. degree in Electrical and Computer Engineering from the University of Victoria, Victoria, BC, Canada in 1989. From 1989 to 1991 he was employed as a Defence Scientist at Defence Research Establishment Ottawa, Ottawa, ON, Canada. He has held academic positions at Carleton University, Ottawa, and the University of Canterbury, Christchurch, New Zealand. He joined the University of Victoria in 1999 and is a Professor in the Department of Electrical and Computer Engineering. He is a Senior Member of the IEEE and a member of the Association of Professional Engineers of Ontario, Canada. In 2002, he became a Fellow of the Engineering Institute of Canada. His research interests include information theory and communication theory, algebraic coding theory, cryptography, construction of optimal codes, turbo codes, spread spectrum communications, space-time coding and ultra wideband communications.     

Exploiting Mobility for Energy Efficient Data Collection in Wireless Sensor Networks

We analyze an architecture based on mobility to address the problem of energy efficient data collection in a sensor network. Our approach exploits mobile nodes present in the sensor field as forwarding agents. As a mobile node moves in close proximity to sensors, data is transferred to the mobile node for later depositing at the destination. We present an analytical model to understand the key performance metrics such as data transfer, latency to the destination, and power. Parameters for our model include: sensor buffer size, data generation rate, radio characteristics, and mobility patterns of mobile nodes. Through simulation we verify our model and show that our approach can provide substantial savings in energy as compared to the traditional ad-hoc network approach. Sushant Jain is a Ph.D. candidate in the Department of Computer Science and Engineering at the University of Washington. His research interests are in design and analysis of routing algorithms for networking systems. He received a MS in Computer Science from the University of Washington in 2001 and a B.Tech degree in Computer Science from IIT Delhi in 1999. Rahul C. Shah completed the B. Tech (Hons) degree from the Indian Institute of Technology, Kharagpur in 1999 majoring in Electronics and Electrical Communication Engineering. He is currently pursuing his Ph.D. in Electrical Engineering at the University of California, Berkeley. His research interests are in energy-efficient protocol design for wireless sensor/ad hoc networks, design methodology for protocols and next generation cellular networks. Waylon Brunette is a Research Engineer in the Department of Computer Science and Engineering at the University of Washington. His research interests include mobile and ubiquitous computing, wireless sensor networks, and personal area networks. Currently, he is engaged in collaborative work with Intel Research Seattle to develop new uses for embedded devices and RFID technologies in ubiquitous computing. He received a BS in Computer Engineering from the University of Washington in 2002. Gaetano Borriello is a Professor in the Department of Computer Science and Engineering at the University of Washington. His research interests are in embedded and ubiquitous computing, principally new hardware devices that integrate seamlessly into the user’s environment with particular focus on location and identification systems. His principal projects are in creating manageable RFID systems that are sensitive to user privacy concerns and in context-awareness through sensors distributed in the environment as well as carried by users. Sumit Roy received the B. Tech. degree from the Indian Institute of Technology (Kanpur) in 1983, and the M. S. and Ph. D. degrees from the University of California (Santa Barbara), all in Electrical Engineering in 1985 and 1988 respectively, as well as an M. A. in Statistics and Applied Probability in 1988. His previous academic appointments were at the Moore School of Electrical Engineering, University of Pennsylvania, and at the University of Texas, San Antonio. He is presently Prof, of Electrical Engineering, Univ. of Washington where his research interests center around analysis/design of communication systems/networks, with a topical emphasis on next generation mobile/wireless networks. He is currently on academic leave at Intel Wireless Technology Lab working on high speed UWB radios and next generation Wireless LANs. His activities for the IEEE Communications Society includes membership of several technical committees and TPC for conferences, and he serves as an Editor for the IEEE Transactions on Wireless Communications.     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Vehicle Velocity Estimation Based on RSS Measurements

This paper presents a technique which is based on pattern recognition techniques, in order to estimate Mobile Terminal (MT) velocity. The proposed technique applies on received signal strength (RSS) measurements and more precisely on information extracted from Iub air interface, in wIDeband code-division multiple access (WCDMA) systems for transmission control purposes. Pattern recognition is performed by HIDden Markov Model (HMM), which is trained with downlink signal strength measurements for specific areas, employing Clustering LARge Applications (CLARA) like a clustering method. Accurate results from a single probe vehicle show the potential of the method, when applied to large scale of MTs. Theodore S. Stamoulakatos is a Senior Research Associate with the Department of Electrical and Computer Engineering at National Technical University of Athens (NTUA). He received his B.Sc. in Mathematics from University of the Aegean, Greece, in 1997, and the M.Sc. in Computer Applications from Dublin City University, Ireland, in 1999 with scholarship from the Irish Ministry of Education. On April ’05 he received his Ph.D. degree from the Department of Electrical Engineering and Computer Science of the National Technical University of Athens. He has been lecturing in DCU various courses including Algorithms & Data Structures, Computer Systems, and Advanced Network Management to both undergraduate and postgraduate students. During his research in NTUA, he has been actively involved in many European and National projects that match his research interests. Both his academic as well as his industrial experience (four years in OTEnet S.A.) allow him to publish several papers in journals and international conferences, which are in the fields of Mobile and Personal Communication Networks, Active Networks, Location Based Services as well as Network and Service Management. Dr. Stamoulakatos is a member of the IEEE. Antonis E. Markopoulos obtained his degree in Informatics and Telecommunications Engineering from University of Athens, Greece in 2000. During his studies he participated in various research projects dealing with the management of fixed and wireless networks. He has also industrial experience for 2 years in INTRASOFT International S.A participating in several projects, national and European. He received his PhD in the field of Cellular and Wireless Communication from the National Technical University of Athens in 2005, where he is working as a Senior Research Engineer in the Telecommunication Laboratory. He has published several papers in journals, international conferences and book chapters. His research interests are in the fields of cellular and wireless networks of present and future generation (4G, WLAN/WPAN, WiMAX) and more specific in the areas of radio resource management and security. He has been mainly involved in many European (IST-CELLO, IST-PACWOMAN, IST-MAGNET, a.o) and National (Greek IST, GGRT) projects. Dr Markopoulos is a member of the IEEE and of the Greek Association of Mechanical and Electrical Engineers. Miltiades E. Anagnostou was born in Athens, Greece, in 1958. He received the Electrical Engineer’s Diploma from the National Technical University of Athens (NTUA) in 1981. In 1987 he received his PhD in the area of computer networks. Since 1989 he has been teaching at the Electrical and Computer Engineering School of NTUA, where he is currently a Full Professor. He teaches courses on modern telecommunications, computer networks, formal specification, stochastic processes, and network algorithms. His research spans several fields, including broadband networks, mobile and personal communications, service engineering, mobile agents, pervasive computing, network algorithms and queuing systems. He is a member of the IEEE and the ACM. Michael E. Theologou received the degree in Electrical Engineering from Patras University and his Ph.D. degree from the Department of Electrical Engineering and Computer Science of the National Technical University of Athens. Currently he is a Professor at National Technical University of Athens, Department of Electrical and Computer Engineering conducting teaching and research in the wider area of Telecommunication Networks and Systems. His research interests are in the fields of Mobile and Personal Communication Networks, Computer Networks, Quality of Service. He has many publications in the above areas.     

Legitimate Skew Clock Routing with Buffer Insertion

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective. Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design. Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms. Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on. Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.     

VHDL Implementation of the Fast Wavelet Transform

In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two-channel subband coder, is described. The units were simulated, synthesized, and optimized using Mentor^? design tools. The final design was verified with VHDL test benches and Matlab image processing tools. Results of the decomposition for color images validate the design. Utilizing a clock frequency of 25 MHz, a time period of 45 ms was estimated for the decomposition process of a 640 × 480 color image, which makes it feasible for real time video compression. The size of the layout was found to be within 2.5 × 2.5 mm, which suggests a 40 pin-package tiny frame. Paul Salama received the B.Sc. in Electrical Engineering (First Class Honors) from the University of Khartoum in 1991, and the M.S.E.E. and the Ph.D. degrees from Purdue University in 1993 and 1999, respectively. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI). His research interests include image and video compression, image processing, Transmission of compressed Video, Ill posed problems, and medical imaging. Dr. Salama is a member of SPIE, Tau Beta Pi, and Eta Kappa Nu. Maher E. Rizkalla received his Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1985. From Jan. 1985 to Sep. 1986, he was a Visiting Scientist at Argonne National Laboratory, Argonne, IL while being a Visiting Assistant Professor at Purdue University Calumet. Since 1986 he has been with the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI), where he is Professor of Electrical and Computer Engineering. His research interests include solid-state electronics, VLSI design as applied to DSP, electromagnetics, and engineering education. He has published over 100 papers in these areas. He received the outstanding teaching awards in the ECE Department and in the School five times and was the Professor of the Year at Purdue Calumet in 1986. He is the recipient of one NSF grant, and two FIPSE grants, and is COPI of a number of industrial and equipment grants. Dr. Rizkalla is a Senior Member, IEEE, and a Professional Engineer (PE) registered in the State of Indiana. Michael Eckbauer received the M.S.E.E. degree in Electrical Engineering from Indiana University Purdue University Indianapolis (IUPUI) in December 2002. He is currently with GE Medical Systems in Waukesha, Wisconsin.     

The design and evaluation of an end-to-end handoff management protocol

We introduce an efficient protocol for end-to-end handoff management in heterogeneous wireless IP-based networks. The protocol is based on the stream control transmission protocol (SCTP), and employs a soft-handoff mechanism that uses end-to-end semantics for signaling handoffs and for transmitting control messages. The design goal of this protocol is twofold—first, to reduce the home registration delay, and, second, to eliminate the tunnelling cost which exists in current proposals, such as Mobile IP and its derivatives. Furthermore, we propose successive enhancements to the initial mobility management framework for achieving better scalability. We present strong analytical and simulation-based results that show performance improvements over existing approaches. Antonios Argyriou is a Ph.D. candidate in the school of electrical and computer engineering, Georgia Institute of Technology. He received his M.S. degree from the Georgia Institute of Technology in 2003, and the diploma from Democritus University of Thrace in 2001, both in electrical and computer engineering. His research interests spawn in all aspects of computer networking while specific interests include wireless networks and multimedia communications. He is a student member of IEEE and ACM. Vijay Madisetti is a professor of electrical and computer engineering at the Georgia Institute of Technology. He splits his time among teaching, research and entrepreneurship. His interests are design, prototyping, and packaging of electronic systems, virtual prototyping, embedded software systems, and computer networks. He obtained his Ph.D. in electrical engineering and computer science from the University of California at Berkeley. He is a member of the IEEE and the Computer Society.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System

This paper presents the idea of managing the comprising computations of an application performed by an embedded networked system. An efficient algorithm for exploiting the timing slack of building blocks of the application is proposed. The slack of blocks can be utilized by replacing them with slower but cheaper, i.e. better, modules and by assigning the computations to the proper resources. Thus, our approach manages the comprising computations and system resources and can indirectly assist the realtime scheduling of computations on system resources. This is performed without compromising the timing constraints of the application and can lead to significant improvements in power dissipation, computation accuracy or other metrics of the application domain. Our algorithm is well-suited for arbitrary tree computations. Moreover, it delivers solutions that are desirably close to the optimal solution. Experimental results for a number of object tracking applications implemented in an networked system with embedded computation resources, exhibit a significant amount of slack utilization. Soheil Ghiasi received his B.S. from Sharif University of Technology, Tehran, Iran in 1998, and his M.S. and Ph.D. in Computer Science from the University of California, Los Angeles in 2002 and 2004, respectively. Currently, he is an assistant professor in the department of electrical and computer engineering at the University of California, Davis. His research interests include different aspects of Embedded and Reconfigurable system design. Elaheh Bozorgzadeh received the B.S. degree in Electrical Engineering from Sharif University of Technology, Iran in 1998, M.S. degree in Computer Engineering from Northwestern University in 2000, and Ph.D. degree in Computer Science from the University of California, Los Angeles, in 2003. She is currently as assistant professor in the Department of Computer Science at the University of California, Irvine. Her research interest includes VLSI CAD, design automation for embedded systems, and reconfigurable computing. She is a member of ACM and IEEE. Karlene Nguyen received her B.S. and M.S. from University of California, Los Angeles in 2001 and 2003, respectively. She has been working with Prof. Majid Sarrafzadeh for her M.S. degree. Her research interests include embedded hardware and software design. Majid Sarrafzadeh received his B.S., M.S. and Ph.D. in 1982, 1984, and 1987 respectively from the University of Illinois at Urbana-Champaign in Electrical and Computer Engineering. He joined Northwestern University as an Assistant Professor in 1987. In 2000, he joined the Computer Science Department at University of California at Los Angeles (UCLA). His recent research interests lie in the area of Embedded and Reconfigurable Computing, VLSI CAD, and design and analysis of algorithms. Dr. Sarrafzadeh is a Fellow of IEEE for his contribution to “Theory and Practice of VLSI Design.” He received an NSF Engineering Initiation award, two distinguished paper awards in ICCAD, and the best paper award in DAC. He has served on the technical program committee of numerous conferences in the area of VLSI Design and CAD, including ICCAD, DAC, EDAC, ISPD, FPGA, and DesignCon. He has served as committee chairs of a number of these conferences. He is on the executive committee/steering committee of several conferences such as ICCAD, ISPD, and ISQED. He is the program committee chair of ICCAD 2004. Professor Sarrafzadeh has published approximately 250 papers, is a co-editor of the book “Algorithmic Aspects of VLSI Layout” (1994 by World Scientific), and co-author of the book “An Introduction to VLSI Physical Design” (1996 by McGraw Hill). Dr. Sarrafzadeh is an Associate Editor of ACM Transaction on Design Automation (TODAES) and an Associate Editor of IEEE Transactions on Computer-Aided Design (TCAD) and ACM Transactions on design Automation (TODAES). Dr. Sarrafzadeh has collaborated with many industries in the past fifteen years including IBM, Motorola, and many CAD industries. He is the architect of the physical design subsystem of Monterey Design Systems main product. He is a co-founder of Hier Design, Inc.     

A New Efficient Block-Matching Algorithm for Motion Estimation

This paper presents a new full-search block-matching algorithm: Multi-stage Interval-based Motion Estimation algorithm (MIME). The proposed algorithm is a block based motion estimation algorithm that utilizes successive elimination technique. We define two approximate functions, as the upper and lower boundaries of the interval that includes the Conventional distortion metric SAD. Each stage in the proposed algorithm; except for the last stage; incorporates low resolution pixels for the boundary functions calculations. The final stage is a full resolution block matching stage. MIME has a high probability of finding the optimal motion vector at any stage of the algorithm. The proposed algorithm reduces the computational complexity by successively eliminating non-candidate blocks from the search window at each stage. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented in this paper. Simulation results on benchmark video sequences shows that MIME algorithm eliminates almost 88% of the candidate blocks after only two interval based stages. Hanan Ahmed Hosny Mahmoud obtained the B.Sc. of Computer Science from Faculty of Engineering, University of Alexandria in 1986. She obtained her M.Sc. in Computer Science from Faculty of Engineering, University of Alexandria in 1991. She obtained the M.Sc. in Computer Engineering from University of Louisiana at Lafayette in 1999 and the Ph.D. in Computer Engineering from University of Louisiana at Lafayette in 2001. Currently, she is working as an Assistant Professor in the Faculty of Engineering, University of Alexandria. Sumeer Goel received the B. Tech degree in electronics and communications engineering from Punjab Technical University, Punjab, India, in 2001. He received the M.S. degree in computer engineering from University of Louisiana at Lafayette, Lafayette, LA, in 2003 where he is continuing his education towards Ph.D. degree in computer engineering. His research interests are low-power and high noise tolerance VLSI circuit and architecture design for digital signal processing applications. Mohsen Shaaban received his B.S. degree in electrical engineering and communications from the University of Alexandria, Egypt, in 1998. In 2001, he joined the University of Louisiana at Lafayette (ULL) as a teaching and research assistant at the Center For Advanced Computer Studies (CACS), the VLSI Research Lab. He received his M.S. degree in the field computer engineering from ULL in 2003. Currently, he is pursing his Ph.D. degree in the same field. His research interests include Digital VLSI circuit design, CAD tools and Video processing applications. Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Medium Access Control for Integrated Multimedia Wireless Access with the Use of a Video Packet Discard Scheme

A well designed Medium Access Control (MAC) protocol for wireless networks should provide an efficient mechanism to share the limited bandwidth resources, and satisfy the diverse and usually contradictory Quality of Service (QoS) requirements of each traffic class. In this paper a new MAC protocol for next generation wireless communications is presented and investigated. The protocol uses a combined Packet Discard/Forward Error Correction scheme in order to efficiently integrate MPEG-4 videoconference packet traffic with voice, SMS data and web packet traffic over a noisy wireless channel of high capacity. Our scheme achieves high aggregate channel throughput in all cases of traffic load, while preserving the Quality of Service (QoS) requirements of each traffic type, and is shown to clearly outperform DPRMA, another efficient MAC protocol proposed in the literature for multimedia traffic integration over wireless networks. Dr. Polychronis Koutsakis was born in Hania, Greece, in 1974. He received his 5-year Diploma in Electrical Engineering in 1997 from the University of Patras, Greece and his MSc and Ph.D. degrees in Electronic and Computer Engineering in 1999 and 2002, respectively, from the Technical University of Crete, Greece. He was a Visiting Lecturer at the Electronic and Computer Engineering Department of the same University for three years (2003–2006). He is currently an Assistant Professor at the Electrical and Computer Engineering Department of McMaster University, Canada. His research interests focus on the design, modeling and performance evaluation of computer communication networks, and especially on the design and evaluation of multiple access schemes for multimedia integration over wireless networks, on call admission control and traffic policing schemes for both wireless and wired networks, on multiple access control protocols for mobile satellite networks, wireless sensor networks and powerline networks, and on traffic modeling. Dr. Koutsakis has authored more than 45 peer-reviewed papers in the above mentioned areas, has served as a Guest Editor for an issue of the ACM Mobile Computing and Communications Review, as a TPC member for conferences such as IEEE GLOBECOM, IEEE LCN and IEEE PerCom, will serve as Session Chair for the IEEE GLOBECOM 2006 Symposium on Satellite & Space Communications and serves as a reviewer for most of the major journal publications focused on his research field. Moisis Vafiadis was born in Elefsina, Greece, in 1980. He has recently completed his studies towards the Diploma in Electronic Engineering at the Technological Educational Institute of Crete, Greece. His research interests focus on wireless personal communication networks, and especially on the MAC layer and on the development and testing of wireless multimedia applications.     

A secure incentive protocol for mobile ad hoc networks

The proper functioning of mobile ad hoc networks depends on the hypothesis that each individual node is ready to forward packets for others. This common assumption, however, might be undermined by the existence of selfish users who are reluctant to act as packet relays in order to save their own resources. Such non-cooperative behavior would cause the sharp degradation of network throughput. To address this problem, we propose a credit-based Secure Incentive Protocol (SIP) to stimulate cooperation among mobile nodes with individual interests. SIP can be implemented in a fully distributed way and does not require any pre-deployed infrastructure. In addition, SIP is immune to a wide range of attacks and is of low communication overhead by using a Bloom filter. Detailed simulation studies have confirmed the efficacy and efficiency of SIP. This work was supported in part by the U.S. Office of Naval Research under Young Investigator Award N000140210464 and under grant N000140210554. Yanchao Zhang received the B.E. degree in Computer Communications from Nanjing University of Posts and Telecommunications, Nanjing, China, in July 1999, and the M.E. degree in Computer Applications from Beijing University of Posts and Telecommunications, Beijing, China, in April 2002. Since September 2002, he has been working towards the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, Florida, USA. His research interests are network and distributed system security, wireless networking, and mobile computing, with emphasis on mobile ad hoc networks, wireless sensor networks, wireless mesh networks, and heterogeneous wired/wireless networks. Wenjing Lou is an assistant professor in the Electrical and Computer Engineering department at Worcester Polytechnic Institute. She obtained her Ph.D degree in Electrical and Computer Engineering from University of Florida in 2003. She received the M.A.Sc degree from Nanyang Technological University, Singapore, in 1998, the M.E degree and the B.E degree in Computer Science and Engineering from Xi'an Jiaotong University, China, in 1996 and 1993 respectively. From Dec 1997 to Jul 1999, she worked as a Research Engineer in Network Technology Research Center, Nanyang Technological University. Her current research interests are in the areas of ad hoc and sensor networks, with emphases on network security and routing issues. Wei Liu received his B.E. and M.E. in Electrical and Information Engineering from Huazhong University of Science and Technology, Wuhan, China, in 1998 and 2001. In August 2005, he received his PhD in Electrical and Computer Engineering from University of Florida. Currently, he is a senior technical member with Scalable Network Technologies. His research interest includes cross-layer design, and communication protocols for mobile ad hoc networks, wireless sensor networks and cellular networks. Yuguang Fang received a Ph.D. degree in Systems Engineering from Case Western Reserve University in January 1994 and a Ph.D degree in Electrical Engineering from Boston University in May 1997. He was an assistant professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology from July 1998 to May 2000. He then joined the Department of Electrical and Computer Engineering at University of Florida in May 2000 as an assistant professor, got an early promotion to an associate professor with tenure in August 2003 and a professor in August 2005. He has published over 150 papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He has served on many editorial boards of technical journals including IEEE Transactions on Communications, IEEE Transactions on Wireless Communications, IEEE Transactions on Mobile Computing and ACM Wireless Networks. He is a senior member of the IEEE.