采用计数器存储权值的人工神经网络的实现

文中提出了一种采用计数器存储权值的人工神经网络的实现方案。数字权值采用计数器存储,突触电路和神经元电路用模拟电路来实现。数字权值经脉冲宽度调制电路转换为脉冲信号作为模拟突触电路的输入信号。因而权值可以长期存储,对权值的修改易于实现,突触神经元电路结构简单,融合了人工神经网络模拟实现和数字实现的优点。对于智能计算机的实现具有重要的意义。     

Recovery of hidden information through synaptic dynamics

The role of synaptic dynamics in processing neural information is investigated in a neural information channel with realistic model neurons having chaotic intrinsic dynamics. Our neuron models are realized in simple analogue circuits, and our synaptic connections are realized both in analogue circuits and through a dynamic clamp program. The information which is input to the first chaotic neuron in the channel emerges partially absent and partially 'hidden'. Part is absent because of the dynamical effects of the chaotic oscillation that effectively acts as a noisy channel. The 'hidden' part is recoverable. We show that synaptic parameters, most significantly receptor binding time constants, can be tuned to enhance the information transmission by the combination of a neuron plus a synapse. We discuss how the dynamics of the synapse can be used to recover 'hidden' information using average mutual information as a measure of the quality of information transport.     

带扰动的变频正弦混沌神经网络研究

为了研究变频正弦混沌神经网络(FCSCNN)的抗扰动能力,在该混沌神经元的内部状态中分别引入三角函数和小波函数扰动项,提出了带扰动的变频正弦混沌神经元模型。给出了该混沌神经元的倒分岔图及Lyapunov指数的时间演化图,分析了其动力学特性。利用该模型构建了新型暂态混沌神经网络,通过选择不同的扰动系数,将其应用于函数优化和组合优化问题上。仿真实验表明,在适当的扰动系数下,变频正弦混沌神经网络能够有效地解决函数优化和组合优化问题,体现了该模型具有较强的鲁棒性和抗扰动能力。     

A two-variable silicon neuron circuit based on the Izhikevich model

The silicon neuron is an analog electronic circuit that reproduces the dynamics of a neuron. It is a useful element for artificial neural networks that work in real time. Silicon neuron circuits have to be simple, and at the same time they must be able to realize rich neuronal dynamics in order to reproduce the various activities of neural networks with compact, low-power consumption, and an easy-to-configure circuit. We have been developing a silicon neuron circuit based on the Izhikevich model, which has rich dynamics in spite of its simplicity. In our previous work, we proposed a simple silicon neuron circuit with low power consumption by reconstructing the mathematical structure in the Izhikevich model using an analog electronic circuit. In this article, we propose an improved circuit in which all of the MOSFETs are operated in the sub-threshold region.     

Two digital circuits for a fully parallel stochastic neural network

This paper presents two digital circuits that allow the implementation of a fully parallel stochastic Hopfield neural network (SHNN). In a parallel SHNN with n neurons, the n*n stochastic signals s (ij) pulse with probability which are proportional to the synapse inputs, are simultaneously available. The proposed circuits calculate the summation of the stochastic input pulses to neuron i(F(i)=Sigma(j) s(ij)). The resulting network achieves considerable speed up with respect to the previous network.     

A programmable analog VLSI neural network processor forcommunication receivers

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.     

Hysteresis modeling based on the hysteretic chaotic neural network

The hysteresis activation function is proposed, and a novel hysteretic chaotic neuron model is constructed by the function. It is shown that the model may exhibit a complex dynamic behavior. On the basis of this neuron model, we propose a novel neural network, which can be applied to hysteresis system modeling. We demonstrate the advantages of the network by experimental results.     

Pulse-stream VLSI neural networks mixing analog and digitaltechniques

The pulse-stream technique, which represents neural states as sequences of pulses, is reviewed. Several general issues are raised, and generic methods appraised, for pulsed encoding, arithmetic, and intercommunication schemes. Two contrasting synapse designs are presented and compared. The first is based on a fully analog computational form in which the only digital component is the signaling mechanism itself-asynchronous, pulse-rate encoded digital voltage pulses. In this circuit, multiplication occurs in the voltage/current domain. The second design uses more conventional digital memory for weight storage, with synapse circuits based on pulse stretching. Integrated circuits implementing up to 15000 analog, fully programmable synaptic connections are described. A demonstrator project is described in which a small robot localization network is implemented using asynchronous, analog, pulse-stream devices.     

PWM型VLSI神经网络在故障诊断中的应用

An improved pulse width modulation (PWM) neural network VLSI circuit for fault diagnosis is presented, which differs from the software-based fault diagnosis approach and exploits the merits of neural network VLSI circuit. A simple synapse multiplier is introduced, which has high precision, large linear range and less switching noise effects. A voltage-mode sigmoid circuit with adjustable gain is introduced for realization of different neuron activation functions. A voltage-pulse conversion circuit required for PWM is also introduced, which has high conversion precision and linearity. These 3 circuits are used to design a PWM VLSI neural network circuit to solve noise fault diagnosis for a main bearing. It can classify the fault samples directly. After signal processing, feature extraction and neural network computation for the analog noise signals including fault information, each output capacitor voltage value of VLSI circuit can be obtained, which represents Euclid distance between the corresponding fault signal template and the diagnosing signal, The real-time online recognition of noise fault signal can also be realized.     

类脑神经网络与神经形态器件及其电路综述

为了系统地了解类脑神经网络电路,在对类脑神经网络进行简要介绍的基础之上,重点阐述两种类别的神经形态器件及功能,包括不同类型的浮栅管和不同工艺材料的忆阻器来模拟单个神经元和突触可塑性功能;然后,以神经形态器件为基础,分别介绍了基于浮栅管和忆阻器实现神经网络电路;最后总结当前神经形态器件及类脑神经网络芯片存在的问题,并对有关类脑计算研究方向进行了展望.     

Decision models for designing and planning private communication networks

We consider the recently developed reconfigurable digital data networks consisting of T1/T3 circuits and Digital Crossconnect Systems (DCSs). A DCS is a device to patch base channels electronically from one T1/T3 circuit to another with a negligible queuing delay at the connecting node. We present new decision models for the design and circuit leasing policies of such digital backbone networks. Our model takes advantage of the special capabilities of the DCS technology and is likely to result in remarkable economic gains for the private network users. The formulation and analyses presented here simultaneously address the following problems: physical link and capacity selection, logical network configuration and channel assignment, and traffic routing on the logical network. The problem formulation results in a large-scale non-linear mixed integer program, and we propose an efficient solution methodology employing Lagrangean relaxation and subgradient optimization. Several numerical results illustrate the utility of our approach for these complex problems. We show that the economies of scale built into the tariff structure of these digital networks can be successfully exploited, and that the inherent flexibility of DCSs leads to logical networks that are dramatically different from their underlying physical topologies.     

基于混沌神经网络的发电机定子绕组匝间短路故障诊断

本文采用耦合的混沌振荡子作为单个混沌神经元构造混沌神经网络模型，用改进Hebb算法设计网络的连接权值。在此基础上，实现了混沌神经网络的动态联想记忆并应用该混沌神经网络模型对发电机定子绕组匝间短路故障进行诊断。结果表明，该种方法有助于故障模式的记     

A scalable optoelectronic neural system using free-space opticalinterconnects

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.     

Analog recurrent decision circuit with high signal-voltage symmetry and delay-time equality to improve continuous-time convergence performance

This paper reports experimental results showing that the recall dynamics of analog associative memories is largely influenced by signal-voltage symmetry of synaptic weights and inverse-noninverse delay-time equality of neurons. We propose a highly symmetric synapse and an equi-delaying neuron. We fabricated an association chip comprised of them to demonstrate a high association performance. In comparison experiments, we also observe large performance degradations when the symmetry or delay equality is deteriorated. We analyze the dynamics based on the statistics of recall results. The proposals and the analysis results are widely applicable to analog recurrent convergence circuits.     

Applying Learning by Examples for Digital Design Automation

This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the inferred models or designs. The resultant models are easy to be implemented in hardware using current VLSI technologies. Our simulation results show that it is often possible to infer a well-defined deterministic model or design from just one sequence of examples. In addition this mechanism is able to handle sequential task involving long-term dependence. This new learning by example mechanism is used as a design by example system for automatic synthesis of digital circuits. Such systems have not previously been successfully developed mainly because of the lack of mechanism to implement them. From artificial neural network research, it seems possible to apply the knowledge gained from learning by example to form a design by example system. However, one of the problems with neural network approaches is that the resultant models are very difficult to be implemented in hardware using current VLSI technologies. By using the mechanism described in this paper, the resultant models are finite state machines that are well suited for digital designs. Several sequential circuit design examples are simulated and tested. Although our test results show that such a system is feasible for designing simple circuits or small-scale circuit modules, the feasibility of such a system for large-scale circuit design remains to be showed. Both the learning mechanism and the design method show potential and the future research directions are provided.     

脉频调制神经网络VLSI的设计及应用

本文提出了一种用于故障诊断识别的改进脉冲频率调制(PFM)VLSI神经网络电路,改进了传统的基于软件的机械故障诊断模式,发挥了神经网络超大规模集成电路(VLSI)的优势.利用单层感知器网络、场效应管电路实现了一种新的数字模拟混合突触乘法/加法器电路,而且该神经网络电路的突触权值不需要学习调整,降低了电路的复杂性.以此电路为基础,设计了进行主轴承噪声故障诊断的神经网络故障识别系统.将含有故障信息的原始噪声信号,经过前置信号处理分析、故障特征值提取和神经网络运算,得出VLSI电路输出端电容的电压——代表待识别信号与模板故障信号的“欧氏距离”,进而判断出故障的类别.经过仿真测试,基于硬件的诊断系统的识别性能接近于基于软件的系统.     

基于FPGA的数字电路进化设计与实现

针对目前演化硬件研究中的关键问题:电路的数学表示方法、遗传算法和快速重构硬件平台,文章建立了一个用于描述数字电路的电路网络演化模型;设计了矩阵组编码算子,改进了精英保留策略;最后基于虚拟可重构技术在FPGA中建立了一个适于演化操作的硬件平台,实现了数字电路的内部进化;实验结果验证了该模型的可行性与有效性,采用的矩阵组编码算子在(8,8,8,4)演化区域内显著提高了电路演化的速度,为演化硬件的进一步发展了提供新的方法。     

A subthreshold MOS neuron circuit based on the Volterra system.

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains.     

A single 1.5-V digital chip for a 106 synapse neuralnetwork

A digital-chip architecture for a 10(6)-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mmx18.6-mm chip by using a 0.5-mum CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed.