Design of a high gain and highly linear common-gate UWB mixer in K-band

In this paper, in order to design a K-band common-gate Gilbert-cell mixer via a 0.18 μm CMOS technology, the π-Network and post-distortion cancellation (PDC) techniques are implemented simultaneously, resulting in the improvement of gain, bandwidth, noise figure and linearity. Also, a new method for implementing the π-Network, using the parasitic capacitances between RF and LO stage nodes, is proposed which improves the mixer performance and makes the mixer design possible at high frequencies. It is shown that the π-Network enhances the gain and bandwidth by generating complex poles in system frequency response without the need for extra power consumption. The suitable location of these poles, which gives rise to high gain and high bandwidth, is discussed and determined by MATLAB simulation. Results of simulation illustrate 3.36 dB improvement in power conversion gain and 2 dB reduction in noise figure at the same power consumption with LO power of ?1 dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6 dB. Also, the power consumption of the mixer together with the designed bias circuit is 9.68 mW at 1.8 V.     

Design of a very linear CMOS transconductance input stage forcontinuous-time filters

A CMOS differential input stage for transconductance amplifiers that combines a low noise excess factor, low input capacitance, and high common-mode rejection ratio with a very good linearity is described. The measured distortion is only 0.2% for a 1-V RMS input signal and only 1% for a 2-V RMS input signal on a test circuit implemented in a standard 3-μm CMOS process, using ±5-V supplies, resulting in over 85 dB of dynamic range. Applications include high-performance continuous-time filters and linear amplifiers     

四类LO信号对CMOS Gilbert混频器增益影响分析

本文深入研究了CMOS Gilbert混频器在四类本振信号(Local Oscillator,LO)作用下的开关模型,提出了相应情况下的混频器电压转换增益修正公式。基于0.25μm标准CMOS工艺的Gilbert混频器仿真结果表明,本文预测的电压增益理论值与仿真结果相差最大为0.08dB,对CMOS混频器的优化设计具有指导意义。     

Transient analysis of electrical and linear charge preset on the input stage of surface CCD's

Transient numerical analysis of electrical signal injection into the surface charge-coupled device (CCD) is given regarding the potential equilibration method. The analysis is composed of the charging and discharging processes of signal charges, characterized by time intervals TCand TDof the respective input pulses. A concept of "setting time TS" explains how the mode of injection converts from the potential equilibration to dynamic injection, and determines an optimum TC. A concept of "residual effect of excess charges" is discussed in relation to sampling effect. The procedure to determine an optimum TDis also proposed. The optimum input timing is divided into two instances in accordance with the degree of the gate lengthL; L > < 5-8µm. For the instances (L > 5-8µm) the timing condition is further split into two cases, depending on the biased potential differenceV_{G1}-V_{BL}. The above conclusions can be applied to setting input pulses and the structure of CCD inputs designed for analog signal processing.     

Phase-referred input: a simple new linear c.c.d. input method

A new method of input linearising a c.c.d. is described. Improvements of 5 to 15dB in linearity over conventional `potential-equilibrium? methods have been obtained.     

Maximizing the output energy of a linear channel with a time- andamplitude-limited input

The problem of maximizing the output energy of a linear time-invariant channel, given that the input signal is time and amplitude limited, is considered. It is shown that a necessary condition for an input μ to be optimal, assuming a unity amplitude constraint is that it satisfy the fixed-point equation=sgn [F(μ)], where the functional F is the convolution of μ with the autocorrelation function of the channel impulse response. It is also shown that all solutions to this equation for which |μ|=1 almost everywhere correspond to local maxima of the output energy. Iteratively recomputing μ from the fixed-point equation leads to an algorithm for finding local optima. Numerical results are given for the cases where the transfer function is ideal low-pass and has two poles. These results support the conjecture that in the ideal low-pass case the optimal input signal is a single square pulse. A generalization of the preceding fixed-point condition is also derived for the problem of maximally separating N outputs of a discrete-time, linear, time-invariant channel     

Design of a CMOS opamp input stage immune to EMI

In this paper the behaviour of a complementary nMOS–pMOS differential pair in the presence of RF interference superimposed on the input terminals is analysed. An intrinsic nonlinearity cancellation mechanism in this structure is demonstrated, and proper design criteria are presented to exploit this mechanism in order to achieve a very high immunity to RF interference. A high-immunity complementary differential pair has been employed as an input stage of a folded cascode operational amplifier and its improved behaviour in the presence of RF interference has been verified by computer simulations.     

Optimal input for stochastic linear discrete systems as a function of input and output variables

An asymptotically optimal input for a plant disturbed by coloured noise is obtained directly in terms of input and output variables.     

Independent control of transconductance gain and input linear rangein a MOS linear transconductance amplifier

A linear self-biasing MOS transconductance amplifier is presented. A linear V-I transfer characteristic is obtained by square-rooting the drain current of a MOS transistor in the saturation region. The main advantage of the circuit is that its transconductance gain and input linear range can be adjusted independently. Simulation results are included to confirm the feasibility of the technique     

一种低压高线性度电流差分跨导放大器

基于TSMC 180 nm工艺库,设计了一款低电压高线性度的电流差分跨导放大器(CDTA,在电路的设计中采用了具有自适应尾电流源偏置结构来提高其线性度。利用Cadence和Spectre软件进行电路设计与仿真。结果显示,在系统典型应用环境下,当Z端的电压在–1.4~+1.3 V变化时,X端的电流变化范围达到–100~+100μA;I_Z/I_P,I_Z/I_N的–3 d B带宽分别为230.5 MHz和236.4 MHz;Z端和X端阻抗分别为8 M?和2.3 M?。该CDTA具有低输入阻抗和高输出阻抗、低电压、高线性度的良好性能,已用于增益可调的有源滤波器设计。     

Short-channel effects on the input stage of surface-channel CCD's

A detailed study of transient signal charge injection into surface-channel charge-coupled devices using a two-dimensional computer model including the source diffusion and the self-induced and fringing field effects has been carried out. The total delay time required to inject a packet of charge into CCD's for a range of device structures was determined. It is found that the maximum clock pulse frequency of operation is determined by the input delay time and not by the speed of charge transfer which is normally assumed. The results of this study are compared with results obtained using a one-dimensional simulation model for charge injection into CCD's. Experimental justification of the one-dimensional model is provided. With the aid of this analysis a design expression for the intrinsic input delay (the delay associated with the fill portion) for short gate surface-channel CCD's is derived and presented in this paper. It is also shown that for short gate devices (L < 8µm) the input delay time due to scooping is about two to four times the intrinsic delay.     

一种改进输入级结构的轨至轨运算放大器设计

基于0.18μm CMOS标准工艺设计了一种改进输入级结构的轨至轨运算放大器电路。该电路由输入级电路、共源共栅放大电路、共源输出电路及偏置电路组成。通过引入正反馈的MOS耦合对管将输入级电路改进为预放大电路,然后对其进行了详细分析,利用Cadence软件对电路进行仿真。仿真结果表明本文结构的低频直流开环增益可以达到80 dB,比相同参数下的普通结构高20 dB左右。相位裕度达到73o,共模输入电压范围满足全幅摆动,共模抑制比低频时可以达到107 dB。     

The transfer characteristic of a linear phase detector when its input signal-noise ratio is small

Phase detectors having sawtooth-type transfer characteristics are superior in some respects to those having cosine-type transfer characteristics. However, the superiority exists only for large input signal-noise ratios. It is shown that for small SNR, the sawtooth characteristic degenerates into a cosine characteristic.     

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz~(1/2), and current noise of less than 0.05 pA/Hz~(1/2).     

一种集成运放输入级用高性能PJFET设计

通过使用肖克莱沟道近似理论和TCAD工具设计了一种可以应用于集成运放输入级的高压超浅结PJFET结构。采用Bi-FET兼容工艺,制作出了顶栅结深约0.1µm,栅漏电小于5pA,击穿电压大于80V,夹断电压在0.8～2.0V范围可调的PJFET。将该类器件及其兼容工艺用于某型号高输入阻抗JFET集成运放的设计与制造,获得了小于50PA的偏置电流,电压噪声小于50nV/Hz1/2,电流噪声小于0.05pA/Hz1/2。     

The linear stage of evolution of electron-hole avalanches in semiconductors

A complete analytical solution of the problem of the linear stage of evolution of electron-hole avalanches in the uniform time-independent electric field E _ext is derived. The theory accounts for the drift, diffusion, and impact ionization of electrons and holes, thus providing a means for calculating the space-time distributions of fields and charges as well as all the basic parameters of the avalanches up to the onset of nonlinear effects at the time t _a . Formulas for the group velocity of the avalanches and for the velocity of its leading fronts are derived. It is shown that the time t _a must be determined from the condition that the impact ionization coefficient α in the center of the avalanche be reduced by a specified small quantity η. A transcendent equation is derived, which allows the calculation of the time t _a as a function of the quantity η, the unperturbed coefficient α(E _ext), and other parameters of the semiconductor. It is found that, when α(E _ext) is increased by two orders of magnitude, the total number of electron-hole pairs generated up to the point t _a decreases by nearly three orders of magnitude.     

低电压CMOS运算放大器输入级的研究

产品的小型化需要低电压、低功耗的集成电路,CMOS技术可以将模拟和数字集成在一起,数字电路易满足要求,但模拟电路会产生许多问题,本文介绍低电压CMOD模拟集成运算放大器输入级所面临的问题以及解决的方法。