Optimum doping profile of power MOSFET epitaxial layer

The epitaxial layer resistance of a MOSFET can be slightly reduced by using an optimum doping profile, which exhibits a minimum in the upper half of the layer when the layer thickness is large compared to the cell-to-ceU spacing. A gradual transition from the n epitaxial layer to the n+ substrate is desirable. When current spreading is significant, the resistance may rise as VB²rather than VB^2.5.     

Vertical current components in integrated injection logic

Analytic expressions representing a double diffused transistor impurity profile are used to calculate the current components in IIL structures. The expression for the hole current is given for IIL structures with the epitaxial layer grown on a wide n⁺substrate and for buried layer structures. It was found that an equivalent recombination velocity at the n-n⁺interface,S_{nn+}, is of order 10²higher in buried layer structures than in structures with the epitaxial layer grown on a wide n⁺substrate for comparable doping levels. Results obtained using the analytic expressions are compared with those obtained using a computer program which includes heavy doping effects and doping level mobility dependence. Both calculated and computed results are also compared with measured currents for a given IIL structure with the epitaxial layer grown on a wide n⁺substrate. The calculated and the computed results are in good agreement with the experimental results.     

微分C—V法和C—V法测量硅外延层杂质纵向分布的指数模型

提出了n/n~+或p/p~+硅外延层电荷密度ρ随x~(n-2)方式变化的正、负指数分布模型。导出了微分C—V法和C—V法杂质浓度纵向分布公式;也导出了两方法的耗尽层宽度公式。引入了n参数[logC—log(V_p—V)直线的斜率负倒数],可免去ASTMF419和SJl551—79逐点测量的麻烦,并使数据处理更为精确。还给出了硅外延层中杂质浓度纵向分布的规律。     

Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

Ion-implanted n+ contacts for Ka band GaAs Gunn-effect diodes

Shallow (<1 ?m) n-type doping profiles with peak carrier concentrations of ? 8 × 1017 cm?3 have been formed by sulphur-ion implantation into vapour-phase GaAs epitaxial layers for improved Gunn-effect-diode contacts. Continuous wave output powers in excess of 250 mW were measured at 35 GHz, with the implanted n+ profile biased either as an electron cathode or anode contact.     

Structural,Electrical, and Optical Properties of 4H–SiC for Ultraviolet Photodetectors

Semiconductors - The results of investigations of initial n-4H–SiC structures by various methods are presented. The structures represent a highly doped n+ substrate with epitaxial layers 5...     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.     

Photoelectrochemical capacitance-voltage measurements of 4H-SiC

Photoelectrochemical capacitance-voltage (PC-V) measurements have been successfully made on 4H-SiC material. The 0.05 M KOH solution used as a Schottky contact etches the material with an average roughness of about one percent of the total average etch depth at an etch rate of 1 μm/h. This capability allows the carrier concentration profile of thicker layers with different doping levels to be analyzed. The PC-V measurements are compared with secondary ion mass spectroscopy. The results show agreement with nitrogen doping in the top epitaxial layer and in the substrate. The PC-V measurement also sees an unknown species diffusing out of the substrate into the nominally undoped buffer layer.     

R.F. sputtered Au-Mo contacts to n-GaAs

Capacitance/voltage and current/voltage measurements of r.f. sputtered Au-Mo contacts to epitaxial n/n+ GaAs indicate that compensating damage centres are introduced into the near-surface region of GaAs during the sputtering process. The concentration of these damage centres may be reduced by annealing. For comparison, the net doping profiles in the GaAs were established via independent thermally evaporated Au contacts to the same epitaxial layer.     

A monolithic integrated schottky diode for microwave mixers

A new type of planar microwave mixer diode was produced on GaAs by a self-aligned process, resulting in high precision and yield. Up to now only planar diodes made by the highly sophisticated process of double selective epitaxy met the requirements of mixer operation at X-band. The new design requires only one epitaxial layer. It takes advantage of the inherent doping profile of the epitaxial layer instead of using two different layers. Microwave measurements showed that parasitic elements in the equivalent circuit can be neglected. This is due to the monolithic integration of the diode into a microstrip line which makes packaging superfluous. A cutoff frequency of 220 GHz was achieved.     

The effect of the elevated source/drain doping profile onperformance and reliability of deep submicron MOSFETs

Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field     

AlGaN中Mg掺杂对蓝光发光二极管光电性质的影响

采用金属有机化学气相沉积技术生长了GaN基多量子阱(MQW)蓝光发光二极管外延片,并采用高分辨率X射线衍射仪(HRXRD)和光致光谱仪(PL)表征晶体质量和光学性能,其他的光电性能由制成芯片后测试获得,目的是研究外延片p型AlGaN电子阻挡层Mg掺杂的优化条件.结果表明,在生长p型AlGaN电子阻挡层的Cp2Mg流量为300 cm3/min时,蓝光发光二极管获得最小正向电压VF,而且在此掺杂流量下的多量子阱蓝光发光二极管芯片发光强度明显高于其他流量的样品.因此可以通过优化AlGaN电子阻挡层的掺杂浓度,来显著提高多量子阱蓝光发光二极管的电学性能和光学性能.     

1300V,1600V高压IGBT的实现

本文基于理论分析和实验研究，分别在ｎ＾－／ｎ＾＋／ｐ＾＋外延和硅单晶基片上实现了１３００Ｖ及１６００Ｖ高压ＩＧＢＴ；并进而证实了获得高压ＩＧＢＴ相互联的关键技术──器件纵向横向几何结构及工作参数的准确计量优化，低缺陷密度高性能厚层硅材料的工艺生长技术，和复合高压终端结构的叠加组合形成。     

On the Determination of Charge Profiles in Epitaxial Layers of ZnSe by Capacitance Measurements

The doping profile in semiconducting epitaxial layers is often deduced from the behavior of the capacitance of a Schottky contact evaporated onto the surface of the layer as a function of the bias voltage. It is shown on the example of Au/ZnSe/GaAs heterostructures that the heterojunction with the substrate in series with this Schottky contact leads to erroneous profiles, if no special care is taken in the choice of the frequency used in measuring the capacitance. This frequency must be chosen below the cutoff frequency which is apparent in the graphs of the capacitance vs the frequency.     

Reduction of 1/f noise in multiplexed linear In/sub 0.53/Ga/sub 0.47/As detector arrays via epitaxial doping

A significant (2-5*) reduction in 1/f noise was observed in In/sub 0.53/Ga/sub 0.47/As photodetector arrays read out by a PMOS multiplexer, when the epitaxial InP cap layer doping was changed from undoped to sulfur-doped n type of about 3*10/sup 16/ cm/sup -3/. A further decrease was observed when the InP buffer layer was also changed from undoped to sulfur-doped n type of about 5*10/sup 17/ cm/sup -3/. Data was presented for the variation of 1/f noise, within a temperature range of 18 degrees C to -40 degrees C. Surface states at the InP cap/SiN interface appears to be the primary source of 1/f noise, with the bulk states at the n/sup -/In/sub 0.53/Ga/sub 0.47/As buffer hetero-interface as a secondary source. Increased n-type doping in the high-bandgap InP cap and buffer layers may reduce electron trapping, and thus 1/f noise. The measured noise spectrum of InGaAs photodetectors varies as f/sup y/ with y being approximately -0.45 for device structures with doped and undoped InP can layers. For a doped InP buffer layer, this value of y is -0.3.<>     

High-power and high-temperature operation of Mg-doped AlGaInP-based red laser diodes

This paper reports on high-power and high-temperature operation of an AlGaInP-based high-power red laser diode with magnesium (Mg)-doped quaternary-alloy cladding layer. The use of Mg dopant with small diffusion coefficient enables abrupt doping profiles as well as high carrier concentrations when compared to conventional zinc (Zn) dopant. It was also found that the metal-organic vapor phase epitaxial (MOVPE) growth of Mg-doped quaternary AlGaInP alloy is not affected by so-called reactor memory effects, while unintentional incorporation of Mg is observed in GaAs after the growth of Mg-doped GaAs layers. The higher carrier concentration in the p-type cladding layer enhanced carrier confinement in the active layer so that device performance at high temperature is improved. The abrupt doping profile suppressing dopant diffusion into the active layer eliminates the nonradiative recombination in the active layer resulting in higher external quantum efficiency. The characteristic temperature of the Mg-doped red laser with a lasing wavelength of 659 nm is as high as 167 K while the Zn-doped laser exhibits a temperature of 127 K. High kink-free output power of 150 mW is achieved at 75/spl deg/C.     

Ion-implanted hyperabrupt junction voltage variable capacitors

Voltage variable capacitors have been fabricated using ion implantation and a PtSi Schottky barrier to obtain a high degree of control over the doping in a hyperabrupt diode structure. Three methods for obtaining the desired doping in the hyperabrupt region have been investigated, including diffusion from a low energy predeposition and higher energy implantations with no diffusion. TheC-Vcharacteristics for two different profiles, made using diffusion to drive in an ion predeposition, agree well with theoretical calculations if a Gaussian diffusion profile peaked at the surface is assumed(D = 2.38 times 10^{-13}cm²/s for phosphorus at 1100°C in an oxygen ambient). It has been found that the device parameter spread of about 7 percent is dominated by nonuniformities in the donor concentration of the epitaxial layer. Parameter variations due to sources other than the epitaxial layer doping are about 3 percent. Low-dose channeling implantations have been made to tailor the profile such that the sensitivity-(dC/C)(V/dV) is nearly constant     

Double-drift IMPATT diodes near 100 GHz

This paper reports the highestxpower (frequency)²IMPATTS produced to date. A CW output power of 380 mW has been achieved at 92 GHz with an efficiency of 12.5 percent. An all-implanted double-drift n⁺-n-p-p⁺silicon structure was fabricated, using a lightly doped epitaxial layer as the starting material. The newly made structure uses a more shallow n⁺contact than previous diodes, and therefore has more equal drift spaces. Small-signal admittance calculations show lower susceptance per unit area in the newly made structure. The shallow contact has allowed the study of unequal dopings in the n- and p-drift spaces. Unequal dopings up to 50 percent can be tolerated with less than 20 percent variation in measured efficiency and output power. Both admittance and breakdown voltage calculations based upon experimentally determined doping profiles and independently measured ionization coefficients were found to be in good agreement with experiment. The doping profiles on both sides of the depletion region were determined byC(V)analysis. The testing of both the old and new structures has been carried out in a microwave circuit having improved mechanical tuning accuracy due to the introduction of a newly designed tuning plunger.     

Ion-implantation and activation behavior of Si in MBE-Grown GaAs on Si substrates for GaAs MESFET's

The suitability of MBE-grown GaAs layers on Si substrates has been studied for ion-implanted GaAs MESFET technology. The undoped as-grown GaAs layers had a carrier concentration below 10¹⁴cm^-3. Uniform Si ion implants into 4-µm-thick GaAs layers on Si were annealed at 900°C for 10 s, using a rapid-thermal-annealing (RTA) system. Both the activation and the doping profile were similar to those obtained in bulk semi-insulating GaAs under similar conditions. The SIMS profiles of Si and As atoms near the GaAs/Si heterointerface were identical before and after the RTA process, indicating negigible interdiffusion during the implant activation. Dual implants of a shallow n+ layer and an n-channel layer were used to fabricate GaAs MESFET's with a recess-gate technology. Selective oxygen ion implantation was used for device isolation. The maximum transconductance obtained was 135 mS/ mm compared to typical values of 150-180 mS/mm obtained in our laboratory on GaAs substrates in similar device structures.     

Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-/spl mu/m-deep with 2-/spl mu/m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 /spl Aring/ of thermal silicon-dioxide film and 2/spl mu/m of polysilicon film. The sheet resistances of N/sup +/ and P/sup +/ diffusion and N/sup +/ -doped polysilicon layers were reduced to 3 to 4 /spl Omega//spl square/ by using the self-aligned TiSi/sub 2/ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi/sub 2/ layer. The 0.5-/spl mu/m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi/sub 2/ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static /spl divide/ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.