Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

Matching input/output (I/O) driver output resistance to transmission line impedance is critical for high-speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage, and temperature variations, that same calibration circuitry may perform improperly. This brief presents an I/O driver design that is less sensitive to process, voltage, and temperature variations. The proposed driver design provides a near linear or flat, output resistance response verses output voltage. Advantages of the proposed I/O driver architecture lie in applications where the output DC operating point may have a large variation, thus, reducing the error in matching output resistance.     

A slew-rate controlled output driver using PLL as compensation circuit

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.     

一种采用SCOVP技术的高频率稳定度Buck变换器

提出了一种采用单周期输出电压预测(SCOVP)技术的自适应导通时间(AOT)控制Buck变换器。该变换器可以在输入输出电压及负载变化时实现频率恒定,并可设置外部电阻使Buck变换器准确工作在高开关频率下。首先分析了传统AOT控制Buck变换器的开关频率产生漂移的原因,并提出了一种采用SCOVP技术的单脉冲计时器(OST)电路。其次通过单周期占空比预测输出电压信息,并根据预测的输出电压和负载电流补偿T_ON时间,实现了Buck的频率稳定。该变换器采用0.18μm BCD工艺进行电路设计。仿真结果表明,在2 MHz开关频率下,负载电流从1 A到5 A变化时,Buck变换器的最大频率变化Δf_SW仅13 kHz,负载平均频率变化Δf_SW/ΔILoad为3.24 kHz/A。同时,变换器频率设置准确度从88%提升到99.35%。     

An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers

An accurate CMOS current source for current-mode low-voltage differential transmitter drivers has been designed and fabricated. It is composed of binary weighted current mirrors with built-in self-calibration circuits. The proposed self-measurement and calibration circuits can calibrate upon the collective effects of different error contributors due to process, power supply, and temperature variations. The design has been fabricated in standard 0.35-/spl mu/m CMOS technology. Measurement results show that the differential output voltage can be self-calibrated to /spl plusmn/1% accuracy with 16% reference current variation, 60% power supply variation, or 13% load resistance variation, respectively.     

一种新颖的多值基准输出缓冲器设计

对比分析了不同结构的传统多值基准输出缓冲器,提出了一种新颖的多值基准输出缓冲器结构.采用PMOS输出结构提高了输出电压摆幅,利用低输出阻抗结构加快了瞬态响应速度,解决了传统结构无法兼具高输出与快响应的矛盾,电路功耗低、易补偿.基于0.15 μm标准CMOS工艺,用Hspice软件对电路进行仿真.仿真结果表明,当电源电压...     

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

A tunable CMOS-DRAM voltage limiter with stabilized feedbackamplifier

The authors present two developments for a CMOS-DRAM voltage limiter: a precise internal-voltage generator, and a stabilized driver composed of a feedback amplifier with compensation. The voltage limiter's features include generating a PMOS-V_T difference, being capable of voltage tuning with fuse trimming, and compensation in the driver circuit through zero insertion. It provides a voltage impervious to supply-voltage and substrate-voltage boundings, temperature variation, and process fluctuation, while ensuring the feedback-loop stability with a phase margin of 55° for a time-dependent load of DRAM circuit. The proposed circuits are experimentally evaluated through their implementation in a 16-Mb CMOS DRAM. A temperature dependency of 1.4 mV/°C and a voltage deviation within ±10% for process fluctuation are achieved. The voltage is stabilized within ±3% for V_CC bounce and ±10% for memory operation     

一种減少TFT显示板上闸驱动器输出电晶体应力效应的设计

为了降低 TFT-LCD 闸驱动电路中电晶体因畏期承受高的闸电压应力造成門限(Threshold)电压之劣化现象,本研究中探用双下拉结构与放电路径方式设计了一个高可靠性的 TFT-LCD 面板整合(On-panel)闸驱动电路.其中,交互道通的双下拉结构减少下拉电晶体的承力晴同;放电路径则将输出驱动电晶体高的闸极电压及時洩放.所提结构由台积电(TSMC)0.35 μm CMOS 制程技术制作之评估晶片经测试显示,门限电压的偏移量减少了近 45%,改善效果极为显著.应用到α-SiTFT-LCD 面板整合闸驱动器上,其成效当可预期.     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3sigma clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations.     

大电流、高稳定性的LDO线形稳压器

以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mY以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.     

High voltage output circuit using n- and n-LDMOSFET with thick gate oxide for PDP driver IC

A novel high voltage output circuit with thick-gated LDMOSFETs is proposed to reduce the chip size and to improve the switching speed for the plasma display panels (PDP) driver IC. The chip size of the PDP driver IC using the proposed output circuit is reduced by 35% with a similar falling time compared with the conventional one. The falling time of the proposed output circuit is about 2.5 times faster than that of the conventional one under the same size when the supply voltage and load capacitance are 180 V and 100 pF, respectively.     

Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push–Pull Techniques for Enhancing Transient Performance

An adaptive reference control (ARC) technique is proposed for minimizing overshoot/undershoot voltage and settling time of low-dropout regulators. Linear operation provided by the ARC technique can dynamically and smoothly adjust the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In addition, a dynamic push-pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5%, and 70%, respectively, when load current changes between 1 and 100 mA.     

一种新型的基于pMOS和nMOS阈值电压差的CMOS电压基准源

提出了一种新的纯MOS结构的基准电压源,它利用pMOS和nMOS的阈值电压差来抵消工艺偏差,提高了基准的精度.该电路经过Chartered 0.35mm标准CMOS工艺成功流片,芯片面积为0.022mm2.测试结果表明:输出平均电压在室温下与仿真结果的绝对误差为6mV,在0～100℃范围内温度系数为180ppm/℃,电源调整率为±1.1%.该基准应用于自适应功率管驱动器中.     

A 1-V CMOS Current Reference With Temperature and Process Compensation

A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, V_REF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, I_REF , nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-mum CMOS process. Results from nineteen samples measured over a temperature range of 0degC to 100degC , showed values of I_REF of 144.3 muA plusmn 7% and V_REF of 610.9 mV plusmn 2% due to the combined effect of temperature and process variations.     

A high-temperature, high-voltage, fast response linear voltage regulator

This paper reports a high-temperature integrated linear voltage regulator implemented in a 0.8-??m BCD (bipolar, CMOS and DMOS)-on-silicon-on-insulator process. This step-down voltage regulator converts an unregulated high input DC voltage to a regulated nominal CMOS voltage (i.e. 5?V) for the low-side buffer (pre-driver) and other digital and analog building blocks of a high-temperature integrated gate driver circuit. An error amplifier inside the regulator has been designed using inversion coefficient methodology, and a temperature stable current reference has been used to bias the error amplifier. The linear regulator provides an output voltage of 5.3?V at room temperature and can supply a maximum load current of 200?mA. The linear voltage regulator integrated circuit has been tested at ambient temperatures from 25 to 200?°C with the input voltage varying from 10 to 30?V. A compensation method (pole swap) that extends the range of the system stability has been implemented and analyzed in detail. The simulated unity gain bandwidth can reach approximately 4?MHz when the load current is 200?mA and the measured transient response time is less than 150?nS when the load current is 50?mA and the ambient temperature is 200?°C.     

一种快速响应低压差线性稳压器的设计

介绍了一种应用于DRAM芯片内部供电的新型低压差线性稳压器(LDO)。在传统LDO电路PMOS输出驱动管的栅端增加了一个开关电容电路,根据负载电流使能信号控制耦合电容的接入,使驱动管的栅端耦合到一个正向或者负向的电压脉冲,在负载电流急剧变化时能快速调整过驱动电压,以适应负载电流的变化。仿真结果显示,该电路有利于输出电压的快速稳定,恢复时间缩短了38%以上。采用45 nm DRAM 掩埋字线工艺进行流片。实测结果显示,该LDO输出电压恢复时间在10 ns以内。在DDR3-1600的数据传输速度下,DRAM芯片的数据输出眼图为280 ps,符合JEDEC标准。     

一种可靠的芯片指纹PUF电路

本文引入一种可靠的芯片指纹物理不可克隆函数（Physical Unclonable Function）电路.该PUF包括基于电流饥饿型延迟单元的工艺敏感电路、时间偏差放大器、时间偏差比较器、表决机制与扩散算法五个部分.通过捕获制造工艺的偏差,每一个工艺敏感电路可以稳定产生两路具有微弱延时差的延迟信号,然后比较生成指纹ID;设计一种新型的扩散算法改善PUF的唯一性,引入时间偏差放大器与表决机制增强PUF相对于温度与电源电压变化的稳定性.文中PUF在0.18μm CMOS工艺下实现.仿真结果表明,该PUF的输出具有均匀统计分布特征,同时在温度从-40℃至100℃,电源电压从1.7V至1.9V变化条件下,其输出ID具有97.5%的稳定性.     

A Super Performance Bandgap Voltage Reference with Adjustable Output for DC-DC Converter

1IntroductionIn the modern world,switching mode power suppliesare indispensable in our day-to-day life,which are widelyused in computers,communication equipment,medicalelectronic equipment and aerospace power systems.DC-DCconverters are used to convert an…