Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.     

Sub-40 /spl mu/A continuous-wave lasing in an oxidized vertical-cavity surface-emitting laser with dielectric mirrors

Due to two improvements in cavity design, low-threshold lasing is achieved in oxidized vertical-cavity surface-emitting lasers incorporating upper dielectric distributed Bragg reflectors. Intracavity absorption is reduced by removal of a heavily p-type contact layer and the use of a low-loss MgF-ZnSe upper mirror. We report sub-100 /spl mu/A lasing for a 7-/spl mu/m diameter device, and sub-40 /spl mu/A lasing for a 3-/spl mu/m diameter device. The low-loss cavity design also allows for highly multimode operation at a low-bias current of 600 /spl mu/A in a detuned cavity.     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A compact efficient Schottky collector transistor switch

A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage.     

Convergence and loss bounds for Bayesian sequence prediction

The probability of observing x/sub t/ at time t, given past observations x/sub 1/...x/sub t-1/ can be computed if the true generating distribution /spl mu/ of the sequences x/sub 1/x/sub 2/x/sub 3/... is known. If /spl mu/ is unknown, but known to belong to a class /spl Mscr/ one can base one's prediction on the Bayes mix /spl xi/ defined as a weighted sum of distributions /spl nu/ /spl isin/ /spl Mscr/. Various convergence results of the mixture posterior /spl xi//sub t/ to the true posterior /spl mu//sub t/ are presented. In particular, a new (elementary) derivation of the convergence /spl xi//sub t///spl mu//sub t/ /spl rarr/ 1 is provided, which additionally gives the rate of convergence. A general sequence predictor is allowed to choose an action y/sub t/ based on x/sub 1/...x/sub t-1/ and receives loss /spl lscr//sub x(t)y(t)/ if x/sub t/ is the next symbol of the sequence. No assumptions are made on the structure of /spl lscr/ (apart from being bounded) and /spl Mscr/. The Bayes-optimal prediction scheme /spl Lambda//sub /spl xi// based on mixture /spl xi/ and the Bayes-optimal informed prediction scheme /spl Lambda//sub /spl mu// are defined and the total loss L/sub /spl xi// of /spl Lambda//sub /spl xi// is bounded in terms of the total loss L/sub /spl mu// of /spl Lambda//sub /spl mu//. It is shown that L/sub /spl xi// is bounded for bounded L/sub /spl mu// and L/sub /spl xi///L/sub /spl mu// /spl rarr/ 1 for L/sub /spl mu// /spl rarr/ /spl infin/. Convergence of the instantaneous losses is also proven.     

Tunnel injection active region in an oxide-confined vertical-cavity surface-emitting laser

Data are presented on oxide-confined AlGaAs-GaAs-InGaAs VCSEL's that use high-index half-wave GaAs spacer layers and electronic tunnel injection and confinement. To our knowledge, this is the first demonstration of tunnel injection in a vertical-cavity laser. Threshold currents range from 344 /spl mu/A for a 6.5-/spl mu/m diameter device to 151 /spl mu/A for a 1-/spl mu/m diameter device. The relatively high threshold currents are attributed to a detuned cavity and higher order transverse-mode operation.     

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.     

A new method for pHEMT noise-parameter determination based on 50-/spl Omega/ noise measurement system

A new method for determining the four noise parameters of pseudomorphic high electron-mobility transistors (pHEMTs) based on a 50-/spl Omega/ noise measurement system without a microwave tuner is presented. The noise parameters are determined based on the noise correlation matrix technique by fitting the measured noise figure of the active device. On-wafer experimental verification up to 26 GHz is presented and a comparison with a tuner-based method is given. The scaling rules for noise parameters have also been determined. Good agreement is obtained between simulated and measured results for 2/spl times/20 /spl mu/m, 2/spl times/40 /spl mu/m, and 2/spl times/60 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) 0.25-/spl mu/m double-heterojunction /spl delta/-doped pHEMTs.     

High-performance 1.06-/spl mu/m selectively oxidized vertical-cavity surface-emitting lasers with InGaAs-GaAsP strain-compensated quantum wells

We present the first room-temperature continuous-wave operation of high-performance 1.06-/spl mu/m selectively oxidized vertical-cavity surface-emitting lasers (VCSEL's). The lasers contain strain-compensated InGaAs-GaAsP quantum wells (QW's) in the active region grown by metalorganic vapor phase epitaxy. The threshold current is 190 /spl mu/A for a 2.5/spl times/2.5 /spl mu/m/sup 2/ device, and the threshold voltage is as low as 1.255 V for a 6/spl times/6 /spl mu/m/sup 2/ device. Lasing at a wavelength as long as 1.1 /spl mu/m was also achieved. We discuss the wavelength limit for lasers using the strain-compensated QW's on GaAs substrates.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).     

Nonlinear analysis of GaN MESFETs with Volterra series using large-signal models including trapping effects

Nonlinearities in GaN MESFETs are reported using a large-signal physics-based model. The model accounts for the observed current collapse to determine the frequency dispersion of output resistance and transconductance. Calculated f/sub T/ and f/sub max/ of a 0.8 /spl mu/m/spl times/150 /spl mu/m GaN MESFET are 6.5 and 13 GHz, respectively, which are in close agreement with their measured values of 6 and 14 GHz, respectively. A Volterra-series technique is used to calculate size and frequency-dependent nonlinearities. For a 1.5 /spl mu/m/spl times/150 /spl mu/m FET operating at 1 GHz, the 1 dB compression point and output-referred third-order intercept point are 16.3 and 22.2 dBm, respectively. At the same frequency, the corresponding quantities are 19.6 and 30.5 dBm for a. 0.6 /spl mu/m/spl times/150 /spl mu/m FET. Similar improvements in third-order intermodulation for shorter gatelength devices are observed.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers

We report an interdigitated p-i-n photodetector fabricated on a 1-/spl mu/m-thick Ge epitaxial layer grown on a Si substrate using a 10-/spl mu/m-thick graded SiGe buffer layer. A growth rate of 45 /spl Aring//s/spl sim/60 /spl Aring//s was achieved using low-energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had a threading dislocation density of 10/sup 5/ cm/sup -2/ and a rms surface roughness of 3.28 nm. The 3-dB bandwidth and the external quantum efficiency were measured on a photodetector having 1-/spl mu/m finger width and 2-/spl mu/m spacing with a 25/spl times/28 /spl mu/m/sup 2/ active area. At a wavelength of 1.3 /spl mu/m, the bandwidth was 2.2, 3.5, and 3.8 GHz at bias voltages of -1, -3, and -5 V, respectively. The dark current was 3.2 and 5.0 /spl mu/A at -3 and -5 V, respectively. This photodetector exhibited an external quantum efficiency of 49% at a wavelength of 1.3 /spl mu/m.     

A Micropower CMOS-Instrumentation Amplifier

A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-zero technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4-/spl mu/m double poly process has an offset (/spl tau/) of 370 /spl mu/V, an rms input referred integrated noise (0.5 -f/sub c//2) of 79 /spl mu/V, and consumes only 21 /spl mu/W (f/sub c/ = 8 kHz, V/sub DD/ = 3 V).     

On-chip test circuit for measuring substrate and line-to-line coupling noise

An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 /spl mu/m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise waveform to be reconstructed. On-chip generators ranging in area from 0.25 /spl mu/m/sup 2/ to 1.5 /spl mu/m/sup 2/ produce noise at the receiver decreasing from 3.14 mV//spl mu/m to 0.73 mV//spl mu/m. Open and closed guard rings reduce the noise by 20% and 85%, respectively. Measurement of test circuits manufactured with an epitaxial process-5.5-/spl mu/m-thick epitaxy with 20 /spl Omega//spl middot/cm resistivity on top of a 120 /spl mu/m bulk with 0.03 /spl Omega//spl middot/cm-exhibits a frequency limit of 50MHz below which coupling is insensitive to substrate noise. The difference between experimental results and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.     

1.5 V large-driving class-AB buffer amplifier with quiescent current control

A 1.5 V large-driving class-AB buffer amplifier with quiescent current control suitable for output driver application is proposed. An experimental prototype buffer demonstrated that the circuit draws only 80 /spl mu/A static current, and exhibited the rise time of 0.4 /spl mu/s and fall time of 1 /spl mu/s under a 100 /spl Omega///150 pF load.