Electron Beam Probing—A Solution for MCM Test and Failure Analysis

Electron beam probing is applied for test and analysis of miniaturisedMCM structures. Wiring structures are tested for shorts and opens while fullyassembled MCMs are analysed in order to identify process or design problems[1, 2]. An electron beam short/open tester for laminated substrates has beendeveloped and installed. It allows the test of substrates up to a size of300 × 300 mm² with a spot size ofbelow 30 m without mechanical movement. The system is automated for routineapplication in the fabrication line. Electron beam probe stations are common tools for design verification and debugging ofintegrated circuits. This type of system was adapted to MCMrequirements. The travel range was extended to 80 × 100 mm² to allow for waveform measurements anddiagnostics.     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

适用于软件无线电基带芯片验证的实时原型平台

随着半导体芯片器件规模急剧增长,对芯片的功能验证以及场景验证提出了更多的挑战。而对于基带SOC芯片,挑战则更加显著。基带SOC芯片的设计验证涉及到大量算法、信号处理专用电路、软硬件协同、实时复杂场景等功能评估与验证。一般通用的芯片验证方法(基于测试用例的服务器离线验证以及FPGA原型验证)无法覆盖对基带芯片评估、验证以及测试的要求。针对基带芯片设计验证需求,本文设计并实现了一个基于软件无线电的通用实时原型平台,可满足不同频段、不同协议的基带芯片的算法评估、功能及场景测试需求。本文基于该通用实时原型平台,成功的对一款GPS/BD导航基带芯片进行了实时原型验证,解决了原有离线仿真不能满足的实时场景验证需求,使得基带芯片的验证环境更加贴近真实环境,从而极大的提高了芯片的成功率。     

基于DDS和 FPGA的频率特性测试仪

针对传统频率特性测试仪价格昂贵、体积大、使用不方便等问题提出了基于DDS和FPGA的正弦信号频率特性测试仪。该测试仪由信号源模块、频率相位检测模块、数据处理与控制模块、显示模块4部分组成。该设计采用FPGA控制DDS芯片产生两路相互正交的信号,被测信号与之相乘,经滤波器后检测输出频率、幅度和相位,最后通过显示模块显示。实验结果证明,该频率特性测试仪设计正确可行,且硬件结构简单、体积小、重量轻,能广泛应用于正弦信号的测量,具有较高的应用价值。     

采用电子束探针测试（EBT）的IC单元设计验证技术

本文用电子束探针测试技术对ＩＣ单元电路进行了设计验证,包括功能验证和延迟参数的验证。快速准确地完成了电路内部的故障定位,完成了输入、输出的延迟测量及内部数门的延迟测量,测试结果准确可信。这一技术尝试,为集成电路的设计验证开辟了新的领域。     

智能化超低频频率特性测试仪

阐述了以ＭＣＳ－９８单片机为核心的超低频频率特性测试仪的基本原理，并详细介绍了超低频信号产生电路、频率测量电路、单片机主电路及系统软件设计。该仪器硬件结构简单，软件设计灵活，具有测量范围宽、精度高、使用方便等特点。     

Electron beam testing of ultra large scale integrated circuits

Electron beam testing is finding increasing acceptance within the semiconductor industry as a design analysis tool. In this paper the needs of semiconductor engineers are reviewed. These are then compared with the performance of currently available electron beam test systems as well as with the predicted limitations of the technology. In addition, some recent work is described which has demonstrated superior performance in several ways when compared to current available equipment.     

Failure physics of integrated circuits — A review

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed.In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes.In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.     

Threshold voltage shift due to low energy electrons used in SEM voltage contrast testing

Scanning electron microscope (SEM) voltage contrast testing is being developed for functional design verification, failure analysis, and development of VLSI devices. This technique imparts little electrical loading and requires no physical contact to the chip, both of which are advantages for device testing via internal nodes. One area of concern, however, is the effect of the low-energy electrons (<5 keV) on the transistor parameters. Even for incident electrons below 8 keV which do not penetrate to the gate oxide, a threshold shift has been observed in SOS MOSFET's. The parameter shift is a result of damage to the gate oxide by secondary X-rays generated by the electrons. Limits on the electron energy and fluence are set to minimize the threshold shift during SEM testing. It is found that under the proper conditions sufficient time is available to perform both voltage contrast imaging and nodal waveform measurements without incurring serious threshold voltage shifts.     

Electron beam testing of VLSI circuits assisted by focused ion beam etching

Electron beam testing assisted by focused ion beam etching was examined. Before electron beam testing (EB testing), a small window was made in the passivation film by focused ion beam etching (FIB etching). EB testing was performed through this window. This method was useful because charge buildup on the passivation film is avoided during EB testing. The threshold voltage shift caused by FIB etching was permitted until the residual film thickness on the gate electrode became 0.5μm. This technique was applied to measure the internal voltage waveform of the 256K bit dynamic RAM and confirmed that it was effective for functional testing and failure analysis of VLSI circuits.     

无源RFID标签芯片灵敏度测试方法研究

提出一种测试UHF频段无源RFID标签芯片灵敏度的方法。该方法依据矢量网络分析仪和标签测试仪接口特性阻抗相同的特性,利用矢量网络分析仪测试标签芯片的反射系数,然后通过标签测试仪测试芯片和仪器接口的匹配损耗,进而计算标签芯片的灵敏度。利用该方法对NXP_G2XM芯片和Impinj_Monza3芯片在800～1 000MHz频段内灵敏度进行测试,并将测试结果与datasheet进行对照,分析误差产生的原因,最终证明此方法的准确性。该测试方法采用常规仪器对800～1 000MHz频段内灵敏度进行测试,有重要实际意义。     

基于核的信息安全处理芯片可测性设计

从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计.综合结果显示,所设计的芯片级测试控制器所占用的面积代价非常小.     

一种自动跟踪工频陷波器的研究与设计

介绍了一种新型线性自动跟踪工频陷波器的电路结构。该陷波器应用于电子束曝光机束流测量电路中,用来抑制工频干扰对测量精度的影响。基于对自动跟踪陷波器的基本工作原理分析,陷波器采用了频率/电压转换器与压控带阻滤波器相结合的设计方案,成功地解决了工频频偏对常规工频陷波器滤波性能的严重影响问题。提出了提高抑制工频干扰能力的设计要点和电路调试方法。通过性能指标的测试和长期实际运行应用,证明陷波器满足了电子束测量中对工频干扰进行强抑制的要求,提高了电子束曝光机的制版质量。     

Failure analysis of ULSI circuits using photon emission

A real-time failure analysis technique for ULSI circuits using photon emission is proposed. This technique utilizes a photon detection system combined with a circuit tester. Improved failure detection is achieved because the tester can bias arbitrary blocks in the ULSI chip. Detecting and correct process defects and design errors improves the reliability of the ULSI chip     

基于UVM的HIMAC验证平台的设计

HINOC是一种新型同轴电缆宽带接入技术.HINOC系统的媒质接入控制层核心模块HIMAC的功能验证是整个HINOC 2.0 SOC芯片验证工作的重要组成部分.围绕HIMAC模块的功能验证这一目标,基于通用验证方法学(UniversalVerification Methodology,UVM)机制设计实现了HIMAC模块的功能验证平台,阐述了该平台的结构和实现原理,并利用该平台实现了对HIMAC模块组帧拆帧功能的验证.采用UVM设计的验证平台可重用性强、自动化程度高、层次清晰,有效提高了验证效率,为HIMAC的全面验证和HINOC芯片设计打下了良好基础.     

Architecture and design of a portable protocol tester

The architecture and design of a new generation portable protocol tester that includes most of the capabilities of dedicated protocol test systems and all of the capabilities of commercial portable testers are discussed. The general tester environment and model of the system under test as viewed by the protocol tester are presented. A conceptual model of a protocol tester that captures its main functional requirements is proposed, and the basic performance requirement is presented. The design and structure of a protocol tester that provides the functional and performance capabilities described are outlined. The implementation utilizes custom VLSI multiprocessors and a special-purpose multiprocessing operating system to allow active and passive testing of more than one system simultaneously. The testing software on each processor is organized as a single process consisting of protocol and test entities with event occurrences being implemented as procedure calls aided by hardware subprocessors. All testing methodologies defined by the ISO, including the ferry method, can be implemented and standardized conformance test suites supported. Suggestions for future extensions to the design are offered     

新型散射信道测试机的设计与实现

针对散射信道测试的必要性,设计了能够自动存储测试数据、达到无人值守状态的新型散射信道测试机。介绍了测试机的组成、工作原理和技术优势,详细剖析了基于Nios II的SD卡存储技术和载波频率校准技术的设计思路和实现方案,给出了新型散射信道测试机的性能测试结果。结果表明,新型散射信道测试机测试精度高、检测能力强,自动存储功能稳定可靠。     

A low-cost digital frequency testing approach for mixed-signal devices using ΣΔ modulation

This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma–delta (ΣΔ) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and ΣΔ modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18 μm CMOS implementation of this BIST technique is presented, including some experimental results.     

Maximizing Parallel Testing in an FM Receiver

High volume production environments create great challenges for production testing and verification of Radio Frequency (RF) devices. In this environment, much emphasis is put on parallel testing, or the ability to test multiple devices at the same time using a single tester. In order for this parallelism to become a reality, there is a need for production RF tests to be simplified and reduced to requiring only the simplest test stimulus and analysis. In this paper, we present a new method of measuring the performance of a Frequency Modulation (FM) receiver that requires only a continuous wave signal input in order to eliminate the more costly Signal-to-Noise Ratio test. Using this new technique we will then demonstrate how simplifying this test and adding frequency diversity enables testing of up to 8 devices in parallel using a single tester.     

基于PC104的飞机发控电路测试仪设计

针对飞机机上导弹发控电路的检测需求,提出基于PC104主板的发控电路测试仪设计方案,并从硬件板卡的设计选型思路,软件的测试流程、显示界面设计等方面详细介绍了测试仪的设计思路和实现方法.与以往基于DSP的测试仪相比,该设计具有生产周期短、成本低、维修维护方便等优点.