一种适用于相变存储器锁相环时钟的新型电荷泵

设计了一款低噪声、低功耗的电荷泵,适用于相变存储器驱动电路中的锁相环时钟。与其它结构的电荷泵相比较,此款电路对时钟馈通与电荷注入等干扰免疫力强。根据相变存储器对驱动电路低噪声的性能要求,本电路具有低的热噪声和1/f噪声。仿真结果表明输出电压在0℃~80℃温度范围内最大仅有11mV的偏差,其与PFD所产生的相位噪声在1MHz频率下为-102dB。电路采用40nm CMOS工艺设计,电源电压2.5V,功耗0.125mW,芯片面积60 m×55 m。     

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.     

低频率电荷泵锁相环设计

设计一款音频范围内的电荷泵锁相环,采用动态D触发器鉴频鉴相器及电流舵差分输入电荷泵。压控振荡器采用了对电容充放电的形式产生震荡波形,实现低频输出。采用HHNEC BCD035工艺并用Cadence软件实现仿真,实现250 kHz频率锁定,锁定时间为80μs,锁定时相位差为75 ns且压控振荡器控制电压纹波为5 mV。     

Pump current modulated charge pump PLL

The performance of a charge pump PLL (CP-PLL) is strongly influenced by the pump current magnitude in the pump ON interval. An examination is presented of the effect of linearly increasing pump current on the transient response of a CP-PLL. It has been observed that the process of pump current `modulation' may be used to enhance the transient behaviour of the CP-PLL     

A low jitter supply regulated charge pump PLL with self-calibration

This paper describes a ring oscillator based low jitter charge pump PLL with supply regulation and digital calibration. In order to combat power supply noise, a low drop output voltage regulator is implemented. The VCO gain is tunable by using the 4 bit control self-calibration technique. So that the optimal VCO gain is automatically selected and the process/temperature variation is compensated. Fabricated in the 0.13 μ m CMOS process, the PLL achieves a frequency range of 100-400 MHz and occupies a 190×200 μ m² area. The measured RMS jitter is 5.36 ps at a 400 MHz operating frequency.     

A regulated charge pump with small ripple voltage and fast start-up

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.     

Design of DTMOS based third-order G $$_m$$ m -C filter for fast locking PLL

Analog Integrated Circuits and Signal Processing - Because of its counterintuitive nature, the Negative Group Delay (NGD) remains as an uncommon and unfamiliar electronic function. For this reason,...     

Phase-locked loop design with fast-digital-calibration charge pump

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27–2.88 GHz frequency synthesiser fabricated in TSMC 0.18 μm CMOS 1.8 V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6 V. The proposed PLL has a total power consumption of 22.57 mW and a settling time of 10 μs or less.     

一种快速提取位同步的全数字锁相环

本文提出了一种快速提取位同步的全数字锁相环方案。该方案通过对同步区、反相区以及快慢区的切换,有效地克服了同步时间与量化相位误差的矛盾。具有同步建立时间短、保持时间长、且同步精度高、抗干扰能力强等优点。     

A dynamic analysis of the Dickson charge pump circuit

Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N_min, where N_min is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%     

基于斜坡电荷泵控制的高速低抖动锁相环

本文提出了一种新型高速低抖动锁相环架构。通过实时监测鉴频鉴相器的输出产生线性斜坡电荷泵电流,实现了自适应带宽控制。主要通过在传统锁相环的基础上,巧妙地设计了一个快速启动电路和一个斜坡电荷泵电路。首先,使能快速启动电路实现对环路滤波器的快速预充电;然后当鉴频鉴相器输出的充电电流脉宽超过设定的最小值时,斜坡电流控制电路将线性增加电荷泵电流,从而实现了快速响应和低相位噪声。同时,通过零温度系数电荷泵电流的设计,保证了高速低抖动指标的温度稳定性。所设计的新型锁相环架构已在一款基于0.35 μm的DSP处理芯片中得到验证。测试结果显示所设计斜坡电荷泵锁相环在宽温度范围内使得锁定时间提高了60%,且峰峰值抖动仅有0.3%的良好特性。     

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop(PLL) characterized by a short locking time and low jitter is presented,which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector(PFD) to implement adaptive bandwidth control.This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL.First,the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter...     

微带BPF的一种快速设计方法

基于对现有几种半波长微带BPF设计方法的分析,提出了一种在减少实际调测工作量的同时更快更准确的设计方法,它是在充分利用现有实际电路制备一个模板库的基础上进行适当的变换来实现最终设计。最后提供了一个5阶发夹型滤波器设计实例,实验结果和理论吻合较好。由理论分析和实验结果来看,该方法较传统设计方法不仅更加快捷,而且提高了设计初始值的精确度。     

Research and design of a novel current mode charge pump

To meet the demands for a number of LEDs, a novel charge pump circuit with current mode control is proposed. Regulation is achieved by operating the current mirrors and the output current of the operational transcon ductance amplifier. In the steady state, the input current from power voltage retains constant, so reducing the noise induced on the input voltage source and improving the output voltage ripple. The charge pump small-signal model is used to describe the device's dynamic behavior and stability. Analytical predictions were verified by Hspice sim ulation and testing. Load driving is up to 800 mA with a power voltage of 3.6 V, and the output voltage ripple is less than 45 mV. The output response time is less than 8 μs, and the load current jumps from 400 to 800 mA.     

电流模线性控制电荷泵的研究与设计

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.     

一种可实现锁相环快速自校准的VCO子带选择电路

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.     

Compact sub-hertz OTA-C filter design with interface-trap charge pump

Single-ended and differential operational transconductance amplifier (OTA) configurations are biased with MOSFET interface-trap charge-pumping (ITCP) current generators to achieve very low transconductances for tunable sub-hertz operational transconductance amplifier-capacitor (OTA-C) filter implementation. This paper reviews the basics of ITCP current generation and presents the transconductors and the OTA-C filter configurations based on these transconductors. One of the filters is a low-pass with an experimentally determined lowest cutoff frequency of 0.18 Hz, and the other is a fully differential bandpass with individually tunable lower and upper cutoff frequencies measured down to 0.3 Hz. The former has one 15-pF filter capacitor, and measures 0.0346 mm/sup 2/, whereas the latter contains four such capacitors and occupies 0.188 mm/sup 2/ silicon. Experimental evaluation also includes offset, harmonic distortion, and noise performance.     

A VCO sub-band selection circuit for fast PLL calibration

consumes 0.64 mA at most.     

A new design of a fast barrel switch network

A new implementation of the barrel switch with a speedup of 20-30% as compared to that of the prior barrel switch design is proposed in this paper. Domino CMOS is used to implement the design, which can shift or rotate 32-b data to the left or right by any number of bit positions between 0 and 31. The principles behind the design, timing and area comparisons, layout, simulation, and test results are presented. The area required for laying out the entire circuit was 4.2 mm×3.2 mm. The critical path delay of the circuit was 27.53 ns. This compares very favorably with the 62 ns that was reported by S. M. Kang (1987). A novel feature of the design is the reduction in the number of stages for shifting from six to four, resulting in a 30% increase in speed