Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

A spread spectrum clock generator with a wide frequency and attenuation tuning range based on a third-order error-feedback delta-sigma modulator

In this paper, a novel design of spread-spectrum clock generator (SSCG) with a third-order error-feedback delta-sigma modulator is presented. The proposed SSCG with triangular modulation can generate clocks with center spread ratios of 0.25, 1, 1.75, 2.5, 3.5, 5% and down spread ratios of 0.5, 2, 3.5, 5, 7, 10% over a wide frequency range from 20 to 700 MHz. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Our tests show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 MHz with center spread ratio of 5% can be achieved which is in agreement with the theoretic calculation.     

采用锁频环和锁相环联合捕获的载波跟踪

针对传统锁频环-锁相环跟踪算法中环路状态转换过渡中出现频率阶跃的问题,提出了一种采用锁频环和锁相环联合捕获的方式替代单一锁频环进行捕获的改进算法,同时对环路状态转换的门限进行了推导。仿真结果表明,改进的算法在转换过程中更加平稳,环路性能得到了优化。在信噪比为-10 dB且存在加加速度时跟踪环路在转换时没有出现频率阶跃,达到了设计目的。     

PLL performance comparison with application to spread spectrum clock generator design

This paper presents performance, power and area comparisons of LC vs. Ring VCO-based PLL designs in order to determine the best option for high-speed spread spectrum clock generator (SSCG) designs. Analytical performance, power and area comparisons of LC versus Ring VCO-based PLL designs demonstrate that a Ring VCO can be used to meet the requirements of SATA and SAS applications at rates up to 6 Gbps. The designed SSCG operating frequency range is 2–4.25 GHz with RMS RJ jitter <1.3 and <1.5 pS for non-SSC and SSC modes, respectively, at 3 GHz. The measured EMI reduction is 18 and 21 dB for 2,300 and 4,600 ppm SSC, respectively, also at 3 GHz.     

基于FPGA的自适应锁相环设计

利用锁相环进行载波跟踪是获取本地栽波的一种重要方法,针对锁相环的噪声性能和跟踪速度不能同时达到最优的限制,在锁相环PLL中引入自适应模块,根据环路所处的环境自适应对PLL环路参数做出调整.设计中利用仿真软件MATLAB对自适应锁相环进行仿真,并在FPGA硬件板上利用VHDL编程实现.在载波信号为10 MHz、采样率为80 MHz的条件下,设计的自适应锁相环在噪声水平较小时跟踪速度提高了0.5 μs左右,在噪声水平较高时相位抖动降低了0.01 tad左右.     

基于FPGA的全数字锁相环的设计

简单介绍了全数字锁相环(ADPLL)的结构和工作原理,提出一种在FPGA的基础上可增大全数字锁相环同步范围的设计方法,并给出了部分verilog HDL设计程序的代码和仿真波形。     

基于FPGA的全数字锁相环的设计

简单介绍了全数字锁相环(ADPLL)的结构和工作原理,提出一种在FPGA的基础上可增大全数字锁相环同步范围的设计方法,并给出了部分verilog HDL设计程序的代码和仿真渡形.     

Instantaneous power control of a high speed permanent magnet synchronous generator based on a sliding mode observer and a phase locked loop

This paper proposes an instantaneous power control method for high speed permanent magnet synchronous generators (PMSG), to realize the decoupled control of active power and reactive power, through vector control based on a sliding mode observer (SMO), and a phase locked loop (PLL). Consequently, the high speed PMSG has a high internal power factor, to ensure efficient operation. Vector control and accurate estimation of the instantaneous power require an accurate estimate of the rotor position. The SMO is able to estimate the back electromotive force (EMF). The rotor position and speed can be obtained using a combination of the PLL technique and the phase compensation method. This method has the advantages of robust operation, and being resistant to noise when estimating the position of the rotor. Using instantaneous power theory, the relationship between the output active power, reactive power, and stator current of the PMSG is deduced, and the power constraint condition is analysed for operation at the unit internal power factor. Finally, the accuracy of the rotor position detection, the instantaneous power detection, and the control methods are verified using simulations and experiments.     

基于ADF4106的锁相环设计

信号源作为一种通用测试仪器,是研制、检测与维护众多电子产品的必备工具,而频率合成是信号源的核心组成部分,对信号源整机的功能和指标起着决定性作用,锁相环频率合成可以产生高质量的频率,本设计利用锁相环基本原理,设计出了高性能的频率合成电路.本文详细介绍了某信号源二本振频率3.6GHz的锁相环设计,给出了系统原理图以及关键电...     

Range extension of a digital phase locked loop

This letter presents an improved structure of a digital phase locked loop, offering an extended locking range, a quicker transient response, and a more reduced sampling error than a conventional digital phase locked loop.     

Nonlinear dynamics of a digital phase locked loop

A second-order digital phase-locked loop may exhibit unusual behavior for some parameters due to a fractal boundary between the basin of attraction of the locked fixed point and the attracting basins of coexisting periodic orbits. The usual optimization criterion of the loop parameters using linearized analysis is insufficient, due to coexisting periodic orbits. A new optimization procedure is presented which is based on numerical bifurcation studies. The authors obtain an analytical estimate of average lock time based on the rate of contraction of the phase space in a neighborhood of the fixed point and the size of the phase space that is regular for the underlying Hamiltonian dynamics. The analytical estimate is verified by numerical calculations     

Ageing effect on electromagnetic susceptibility of a phase locked loop

Phase locked loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the analyses of PLL immunity drift after accelerated ageing.     

基于全数字锁相环的基波频率测量算法

本文提出了一种用于电能计量芯片的基波频率测量算法.其创新点是从系统设计出发,把基波频率测量与电能计量中过采样ADC的梳状积分级联抽取滤波(以下简称CIC)过程相结合,利用CIC、正交去调鉴频器、PI调节器和基波频率—CIC抽取率转换器共同构成一个全数字锁相环(以下简称ADPLL).该锁相环可以有效地抑制输入信号中的直流...     

基于科斯塔斯锁相环的光学零差相干接收技术

零差相干光通信能够实现极高的通信速率和接近量子极限的灵敏度,是新一代空间通信领域极具潜力的通信体制。以窄线宽激光器作为本振源,结合90°光学混频技术和科斯塔斯光学锁相环技术,实现了信号光的零差相干接收。试验结果表明,信号光和本振光经过90°光学混频后I、Q两路信号相位差保持90°,科斯塔斯光学锁相环可以长时间实现信号光和本振光之间的相位锁定,接收速率为2Gbps的二进制相移键控(BPSK)信号,试验结果表明,该接收机能够很好地实现基带信号解调。     

基于锁相环（PLL）L波段的频率合成技术

频率合成器是电子设备的核心部件,其性能的优劣影响电子设备的整体性能。本文研究了一种基于锁相环（PLL）L波段的锁相频率技术。其设计方案使用MC145152来实现锁相环路,外加环路滤波器LPF和压控振荡器VCO等器件来实现,具有较强的研究设计价值。     

如何调试锁相环频率合成器

无线电系统会因为各种各样的原因而采用基于锁相环(PLL)技术的频率合成器。PLL的好处包括。     

一种新的三相锁相环的设计研究

针对传统锁相环的设计比较复杂的缺点提出了一种新的三相锁相环。新的锁相环不涉及任何的坐标变换,电路设计更为简单。并且采用CORDIC算法与查表法相结合的方法对三相锁相环进行了优化,进而快速地跟踪相位。最后在Matlab环境下对系统进行了仿真并给出实验结果,其结果表明该方法在谐波失真和三相电压输入失衡时也能准确的进行锁相,进而验证了所提方法的有效性。     

一种针对压缩域信号的新型锁相环技术

针对通信信号压缩采样获得的压缩域信号频率、相位提取问题,提出了一种基于压缩感知的新型锁相环技术。通过深入研究压缩域的信号估计问题,提出了压缩域锁相环路,可以直接在压缩域同步跟踪信号频率和相位变化,不再需要高复杂度的信号重构处理。分析了环路模型及其估计性能,并针对该锁相环可行性和性能分别进行了仿真实验。仿真结果不仅验证了压缩域锁相环的可行性,同时表明该环路能够实现高动态信号的高精度频率提取。压缩域锁相环的应用潜力较大,例如可以作为压缩感知通信接收机的同步解调方法。