An all digital PLL with an active inductor DCO for LTE applications in 0.13 μm CMOS

In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range and to operate at a low-power, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm² using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is −120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

A 5 GHz 90-nm CMOS all digital phase-locked loop

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of −125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm² and the current consumption is 30 mA from a 1.2 V supply.     

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm². The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is ?110.17 dBc/Hz at 1 MHz offset.     

A low-power DCO using inverter interlaced cascaded delay cell

This paper presents a low-power small-area digitally controlled oscillator(DCO) using an inverters interlaced cascaded delay cell(IICDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses IICDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140–600 MHz at the power supply of 1.8 V.The power consumption is 2.34 m W @ a 200 MHz output.     

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.     

A low-power voltage-controlled oscillator with current-switched technique

A low-power voltage-controlled oscillator (VCO) with current-switched technique is presented. The circuit is implemented in 0.18-μm CMOS technology. In the design, a large inductor is used for low-power and low-phase-noise application, whereas a switched capacitor bank and two pairs of MOS varactors are adopted for coarse tuning and fine tuning respectively. The proposed VCO is biased at the boundary of the current and voltage limited region for a good trade-off between power consumption and phase noise. The phase noise of the proposed VCO is reduced in each sub-band by a current-switched technique, and a phase noise improvement of as much as 2.75 dB has been achieved. The proposed VCO has a measured tuning range of 15.2 % from 4.34 to 5.05 GHz and dissipates an average power of 3.78 mW at 1.2 V supply voltage, whereas its measured phase noise and figure of merit FOM_T are ?113.0 dBc/Hz and ?183.7 at 1 MHz offset from the frequency of 4.36 GHz respectively.     

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 $mu$m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.      

A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoM_P without requiring complicate calibration.     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

A calibration-less low error two-point modulation transmitter for 802.15.4 application

A low power phase locked loop (PLL) based transmitter for wireless sensor application is presented in this paper. The transmitter adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and voltage controlled oscillator (VCO) frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a capacitance desensitization technique through combined parallel and serial capacitances with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the transmitter achieves a 5.2 % FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8 mW power. Loop filter and crystal are the only off-chip components.     

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.     

Wide‐Band Fine‐Resolution DCO with an Active Inductor and Three‐Step Coarse Tuning Loop

This paper presents a wide‐band fine‐resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three‐step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three‐step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.     

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.     

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates,DCV and Reconfigurable Schmitt Triggers in 180 nm

Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of \(\mathrm{VDD}=1.8\) v in 180 nm CMOS technology for 64- and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz with 1.604 mW power consumption. Our designs are proper for reconfigurable and multi-standard ADPLL designs.     

A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology

A fast-settling all-digital phase-locked loop (ADPLL) is presented in this paper. We propose two techniques for reducing the settling time of an ADPLL, i.e. the oscillator tuning word (OTW) presetting technique and counter-based mode switching controller (CB-MSC). In the first technique, the OTW is preset in process, voltage, and temperature (PVT) calibration mode (P-mode), which leads to the digitally controlled oscillator being initialized with a frequency closer to the target. In the second technique, the CB-MSC is used to shorten the mode switching time. A prototype 1.9 GHz ADPLL with a 13 MHz reference is implemented in 0.18 μm CMOS process. Measurements show that the proposed techniques reduce the settling time by about 33 %. The proposed ADPLL settles within 130 reference cycles and presents a phase noise of ?116 dBc/Hz@1 MHz.     

An all-digital phase-locked loop with 50-cycle lock time suitablefor high-performance microprocessors

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

一种应用于图像传感器的全数字锁相环设计

针对图像传感器中传统锁相环(PLL)存在的功耗高、抖动大,以及锁定时长等问题,提出了一种基于计数器架构的低功耗、低噪声、低抖动、快速锁定的分数分频全数字锁相环(ADPLL)设计方法。首先,采用动态调节锁定控制算法来降低回路噪声,缩短锁定时间。其次,设计了一个通用单元来实现数字时间转换器(DTC)和时间数字转换器(TDC)的集成,以降低该部分由于增益不匹配引起的抖动。基于180nm CMOS工艺的仿真结果表明,在1.8V电源电压下,该ADPLL能够实现250MHz~2.8GHz范围的频率输出,锁定时间为1.028μs,当偏移载波频率为1MHz时,相位噪声为-102.249dBc/Hz,均方根抖动为1.7ps。