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介绍了一种带ESD瞬态检测的VDD-VSS之间的电压箝位结构,归纳了在设计全芯片ESD保护结构时需要注意的关键点;提出了一种亚微米集成电路全芯片ESD保护的设计方案,从实例中验证了亚微米集成电路的全芯片ESD保护设计. 相似文献
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从全芯片角度出发,采用多电源ESD架构和全芯片ESD设计,对整颗芯片提供全方位的ESD保护,介绍了基于0.18μm CMOS工艺设计的大容量PROM芯片的ESD设计技术。同时,通过对高压编程引脚的ESD加固设计,提高了芯片的整体抗ESD能力。最终产品ESD测试满足项目要求。 相似文献
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通过器件级仿真来评估ESD保护器件的鲁棒性的方法,对ESD电路的关键设计参数进行了研究.通过器件仿真软件MEDICI对栅极到源极接触孔的距离,栅极到漏极接触孔的距离以及栅极的宽度和长度对ESD性能的影响进行了研究,并分析了它们的失效机理.从而得出经验公式,可以在流片前估算出器件的ESD失效电压.通过在设计阶段预测器件的ESD性能可以缩短设计周期,节约成本. 相似文献
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随着CMOS工艺的发展,集成电路元件的尺寸持续减小,芯片的静电放电(ESD)保护设计受到了更大的挑战.从系统的角度出发,采用电压域分别保护后通过隔离器件连接的方法完成了对深亚微米芯片ESD保护系统的设计.设计中分析了传统输出端保护可能存在的问题,并采用稳妥的方法对输出端进行了保护.这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的.设计采用TSMC 0.18 μm工艺,测试结果验证了该设计的有效性. 相似文献
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液晶屏幕越来越多地应用在信息技术设备当中,但是液晶屏幕防静电技术却一直困扰着很多工程师.通过分析液晶屏幕显示原理,结合静电场理论,分析静电放电(ESD)对液晶屏幕的影响,并提供整改实例,简要介绍此类问题的处理方法. 相似文献
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基于静电放电(ESD)应力下深亚微米栅接地N型场效应晶体管(GGNMOS)二次击穿的物理特性,将建立的热击穿温度模型、热源模型与温度相关参数模型相结合,提出了一种新的电热模型,并进行了优化。基于这些模型,可仿真出器件的二次击穿电流值It2(GGNMOS的失效阈值),进而模拟出GGNMOS全工作区域的VD-ID曲线。对两种不同的GGNMOS样品进行模拟仿真,将得到的结果与TLP(传输线脉冲)实验测试的结果相比较,证实了模型的可行性。利用该物理级模型,可快速评估GGNMOS的工艺、版图参数以及脉冲应力宽度对ESD鲁棒性的影响。 相似文献
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Karutz P. Nussbaumer T. Gruber W. Kolar J.W. 《Industrial Electronics, IEEE Transactions on》2010,57(1):52-60
This paper presents an optimization-procedure yielding for minimal acceleration times for different speed ranges using the example of a magnetically levitated slice motor with a large air gap. The optimization is based on a set of analytical equations together with selected 3-D finite element method simulations with the aim to optimize both the stator geometry and the number of drive turns. It is shown that the use of 3-D instead of 2-D simulation tools is obligatory for motors with large air gaps for achieving sufficient simulation accuracy. The relevant equations for the optimization are derived, and the accuracy of the proposed method is verified by measurements on a prototype system. 相似文献
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《Microwave Theory and Techniques》1971,19(7):652-654
A reliable method of tuning and microwave integrated circuit (MIC) line connection which has potential up to X band has been demonstrated. The method utilizes integrable fabricated microcantilever air gaps which are cold-deformed in situ to accomplish trimming. The advantages of this concept are 1) high open-circuit impedance, 2) low short-circuit insertion loss, 3) high trim resolution, 4) low line perturbation, 5) high mechanical stability, and 6) in situ fabrication with the rest of MIC circuitry. 相似文献
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Muchaidze G. Jayong Koo Qing Cai Tun Li Lijun Han Martwick A. Kai Wang Jin Min Drewniak J.L. Pommerenke D. 《Electromagnetic Compatibility, IEEE Transactions on》2008,50(2):268-276
Susceptibility scanning is an increasingly adopted method for root cause analysis of system-level immunity sensitivities. It allows localizing affected nets and integrated circuits (ICs). Further, it can be used to compare the immunity of functionally identical or similar ICs or circuit boards. This paper explains the methodology as applied to electrostatic discharge and provides examples of scan maps and signals probed during immunity scanning. Limitations of present immunity analysis methods are discussed. 相似文献
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《Solid-State Circuits, IEEE Journal of》1977,12(4):363-367
A new process for providing submicron patterning of surfaces is presented. This processing technique, which the authors call the Iso-E process, is capable of producing submicron openings to the surface of materials using conventional photolithographic techniques and processing common to the semiconductor industry. This process can be used equally well with X-ray or electron-beam lithography to provide minimum geometry openings at minimum geometry spacings. 相似文献