A Novel 94-GHz MHEMT Resistive Mixer Using a Micromachined Ring Coupler

In this letter, we present a high performance 94-GHz millimeter-wave monolithic integrated circuit resistive mixer using a 70-nm metamorphic high electron mobility transistor (MHEMT) and micromachined ring coupler. A novel three-dimensional structure of a resistive mixer was proposed in this work, and the ring coupler with the surface micromachined dielectric-supported air-gap microstrip line structure was used for high local oscillator/radio frequency (LO–RF) isolation. Also, the LO–RF isolation was optimized through the simulation. The fabricated mixer has excellent LO–RF isolation, greater than 29 dB, in 2-GHz bandwidth of 93–95GHz. The good conversion loss of 8.9dB was measured at 94GHz. To our knowledge, compared to previously reported W-band mixers, the proposed MHEMT-based resistive mixer using a micromachined ring coupler has shown superior LO–RF isolation and conversion loss.     

High-Performance 94-GHz Single-Balanced Diode Mixer Using Disk-Shaped GaAs Schottky Diodes

We present a high-performance 94-GHz single-balanced monolithic millimeter-wave integrated-circuit (MMIC) mixer using the disk-shaped GaAs Schottky diodes grown on an n/$hbox{n}+$ epitaxial structure. Due to the superior characteristics of the GaAs diodes with high diode-to-diode uniformity, the mixer shows a conversion loss of 5.5 dB at 94 GHz, a 1-dB compression point $(P_{1 hbox{-}{rm dB}})$ of 5 dBm, and high local-oscillator to radio-frequency isolation above 30 dB in an RF frequency range of 91–97 GHz. To our knowledge, the fabricated mixer shows the best performance in terms of conversion loss at 94 GHz and $P_{1 hbox{-}{rm dB}}$ among the W-band MMIC mixers without amplifier circuits.      

A Low-Noise 47-GHz Mixer Using a Permanent Josephson Junction

A new method to produce permanent Josephson junctions for millimeter-wave mixers is reported. In contrast to conventional point contacts which are mechanically unstable and require adjustments after each cooldown, these point contact junctions are set at room temperature, stay mechanically stable, and can be temperature cycled without readjustments. Using these junctions in a modified Sharpless wafer mixer mount, a single-sideband noise temperature of 71 K was measured at 47 GHz. Based on these results, system noise temperatures of less than 100 K are predicted for practical broad-band radiometers, RADAR, and communications receivers up to at least 100 GHz     

一种宽带3dB耦合器的设计与分析

为满足实际工程应用中对宽频器件的迫切需求,采用1/4阶梯阻抗滤波器原理和多节耦合理论对3 dB耦合器进行理论分析,介绍了一种宽带3 dB耦合器的设计,具体说明了该耦合器的结构实现形式和制作工艺,并利用相应的设计原理计算得出其理论尺寸。结合该耦合器的具体物理层实现形式,采用HFSS仿真软件对其建模仿真,按照仿真得到的尺寸进行实物加工,可获得0.8～2.5 GHz工作带宽内驻波比小于1.16、耦合度优于3.25 dB的实测结果,能较好地满足实际工程的需要。     

集总参数宽带3 dB正交定向耦合器的分析方法

介绍一种新的分析集中元件的宽带3 dB定向耦合器的方法。该方法利用奇偶模激励得到具有正交对称平面的本征单端口模型,这种等效使得在定向耦合器的分析过程中,可以直接引用一些现有的结论,利用矢量图示直观地得到各个端口散射参数之间的关系,简化了计算过程。最后对耦合器的拓扑结构的频率特性进行了理论分析和验证,对有关文献进行了扩充。     

一种小型谐波抑制3dB分支耦合器的设计

基于分支线耦合器小型化和谐波抑制特性的要求,提出了一种小型谐波抑制分支线耦合器的设计方法,通过采用等效传输线理论和分形几何结构进行设计。基于此方法,设计了小型谐波抑制3 d B分支线耦合器,并对其进行了实物制作和测试。测试结果表明,该耦合器不仅实现了77.9%的尺寸缩减,而且具有5次谐波抑制的特性。与传统方法相比,设计方法具有尺寸小、谐波抑制特性好、易于制作和集成等优点,可以在无线通信系统中得到广泛应用。     

Analysis and Design of a 3 dB Tunable Lumped-Element Directional Coupler

An analysis of a 3 dB lumped-element directional coupler(LEDC)based on arbitrary terminal impedance is described numerically.To solve the conflicted requirement for broad bandwidth and small size in LEDC,a new structure of coupler is introduced,which can significantly improve bandwidth and whose size is only 3 cm×4 cm on the conditions of the frequency domain of 410 MHz to 490 MHz.The measure results are in good agreement with simulations despite the unexpected resistor loss.     

A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers

An 18-GHz range frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are -65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.     

A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers

A low-power low-noise amplifier (LNA) implemented in 0.18 $mu$m CMOS technology utilizing a self-forward-body-bias (SFBB) technique is proposed for UWB low-frequency band system. By using the SFBB technique, it reduces supply voltage as well as saves additional bias circuits, which leads to low power consumption of 4.5 mW with low supply voltage of 1.06 V for two drain-to-source voltage drops. The complementary architecture and direct coupling technique between the first two stages also save bias circuits. The measurement result shows that the proposed LNA presents a maximum power gain of 16 dB with a good input impedance matching (${rm S}11 < - 12$ dB) and an average noise figure of 2.65 dB in the frequency range of 3–6.5 GHz.      

A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept

A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metal-oxide semiconductor (CMOS) technology. Traveling wave concept was used to minimize the insertion loss at higher frequency and widen the operating bandwidth. The switch exhibits a measured insertion loss of 2.7 -dB, an input 1-dB compression point (input P_{1 dB}) of 15 dBm, and a 29-dB isolation at the center frequency of 77 GHz. The total chip size is only 0.57 times 0.42 mm ² including all testing pads. To our knowledge, this is the first CMOS switch demonstrated beyond 50 GHz, and the performances rival those monolithic microwave integrated circuit switches using standard GaAs PHEMTs     

A 320–360 GHz Subharmonically Pumped Image Rejection Mixer Using Planar Schottky Diodes

This letter presents the design, fabrication and test of an integrated 320–360 GHz subharmonic image rejection mixer using planar Schottky diodes. The integrated circuit uses two separate anti-parallel pairs of diodes mounted onto a single quartz-based circuit. Measurement results give best single sideband (SSB) receiver noise temperatures of approximately 3400 K at 340 GHz, with an image rejection from 7.2 to 24.1 dB over the 320–360 GHz frequency band. This work represents the first demonstration of a Schottky based SSB mixer at submillimeter wavelengths.      

A 26–38 GHz Monolithic Doubly Balanced Mixer

A novel configuration of doubly balanced mixer is presented for operating over the 26–38 GHz band. The monolithic microwave integrated circuit (MMIC) was implemented by GaAs 0.15 $mu$ m pHEMT technology with the compact size of 1 $,times,$2.5 mm $^{2}$. A 180 $^circ$ hybrid circuit and two identical Marchand baluns were employed to achieve good port-to-port isolation. They also have wide band performance, make the mixer more compact, and simplify IF extraction. This mixer has a conversion loss of better than 6 dB, a dc-10 GHz IF bandwidth, and the LO-to-RF and LO-to-IF isolations are better than 20 dB and 29 dB, respectively.      

A 40–50-GHz SiGe 1 : 8 Differential Power Divider Using Shielded Broadside-Coupled Striplines

This paper presents a 1 : 8 differential power divider implemented in a commercial SiGe BiCMOS process using fully shielded broadside-coupled striplines integrated vertically in the silicon interconnect stackup. The 1 : 8 power divider is only 1.12 $,times,$1.5 mm$^{2}$ including pads, and shows 0.4-dB rms gain imbalance and $≪ {hbox{3}}^{circ}$ rms phase imbalance from 40 to 50 GHz over all eight channels, a measured power gain of ${hbox{14.9}} pm {hbox{0.6}}$ dB versus a passive divider at 45 GHz, and a 3-dB bandwidth from 37 to 52 GHz. A detailed characterization of the shielded broadside-coupled striplines is presented and agrees well with simulations. These compact lines can be used for a variety of applications in SiGe/CMOS millimeter-wave circuits, including differential signal distribution, miniature power dividers, matching networks, filters, couplers, and baluns.      

A 23–37 GHz Miniature MMIC Subharmonic Mixer

A novel configuration of subharmonic mixer using an anti-parallel diode pair is presented for operating over the 23-37 GHz band. The monolithic microwave integrated circuit is implemented by GaAs 0.15 mum PHEMT technology with the compact size of 0.85 times 0.85 mm². This mixer employs a directional coupler, LC low-pass filter, and a short stub for isolating three ports corresponding to radio frequency (RF), local oscillation (LO) input, and intermediate frequency (IF) output ports. The directional coupler also provides impedance transformation between the diode pair, RF, and LO ports. This makes the subharmonic mixer more compact and flexible. The best conversion loss of the subharmonic mixer is 9.4 dB, and the LO-to-RF and LO-to-IF isolations are better than 22 and 31 dB, respectively.     

A Novel Reduced-Size Rat-Race Broadside Coupler and Its Application for CMOS Distributed Sub-Harmonic Mixer

A broadband distributed sub-harmonic resistive field effect transistor mixer with a novel modified rat-race broadside coupler using a 0.13-mum CMOS foundry process is presented in this letter. Using the broadside coupler, a reduced-size rat-race is fabricated with a compact size of 110 times 80 mum². From the measurement results, the mixer achieved a conversion loss of 12 dB from 32 to 70 GHz of RF frequency. The passive sub-harmonic mixer has zero power consumption. With the modified rat-race broadside coupler, the mixer achieves a good LO-IF isolation of better than 30 dB and a compact core chip size of 0.55 times 0.4 mm².     

A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump

A 0.5-5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13- CMOS process. The measured root-mean-square and peak-to-peak jitters are 1.06 and 8 ps at 5 GHz, respectively. The power dissipation at 5 GHz is 36 mW for a supply voltage of 1.2 V.     

基于新型超宽带平面巴伦的双平衡混频器

首次基于新型超宽带平面巴伦,设计了工作于超宽带(3.1¹0.6GHz)频段的二极管双平衡混频器。微带到槽线过渡巴伦具有高通性质,可以阻断直流和中频分量,而微带到共面带线(CPS)过渡巴伦可以提供中频和直流回路,二者与交叉二极管对一起构成平面超宽带双平衡混频器。同时,可在中频端口串接宽阻带低通滤波器,进一步改善射频(RF)和本振(LO)端口到中频(IF)端口的隔离度。根据测试结果,当射频和本振信号工作于3.110.6GHz)频段的二极管双平衡混频器。微带到槽线过渡巴伦具有高通性质,可以阻断直流和中频分量,而微带到共面带线(CPS)过渡巴伦可以提供中频和直流回路,二者与交叉二极管对一起构成平面超宽带双平衡混频器。同时,可在中频端口串接宽阻带低通滤波器,进一步改善射频(RF)和本振(LO)端口到中频(IF)端口的隔离度。根据测试结果,当射频和本振信号工作于3.1¹0.6GHz,中频在DC10.6GHz,中频在DC¹00MHz时,变频损耗小于13dB,三个端口之间的隔离度大于25dB。     

A Unique 520–590 GHz Biased Subharmonically-Pumped Schottky Mixer

We report on the design and performance of a novel broadband, biased, subharmonic 520-590 GHz fix-tuned frequency mixer that utilizes planar Schottky diodes. The suspended stripline circuit is fabricated on a GaAs membrane mounted in a split waveguide block. The chip is supported by thick beam leads that are also used to provide precise radio frequency (RF) grounding, RF coupling and dc/intermediate frequency connections. At room temperature, the mixer has a measured double sideband noise temperature of 3000 to 4000 K across the design band.     

A 0–55-GHz Coplanar Waveguide to Coplanar Strip Transition

A broadband coplanar waveguide (CPW) to coplanar strip (CPS) transmission line transition directly integrated with an RF microelectromechanical systems reconfigurable multiband antenna is presented in this paper. This transition design exhibits very good performance up to 55 GHz, and uses a minimum number of dissimilar transmission line sections and wire bonds, achieving a low-loss and low-cost balancing solution to feed planar antenna designs. The transition design methodology that was followed is described and measurement results are presented.     

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $mu$m CMOS

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.