开关电容ΣΔ调制器的行为级建模

在MATLAB的SIMULINK环境下,给出了一套开关电容ΣΔ调制器的时域行为级模型。该模型考虑了SCΣΔ调制器大部分的非线性效应,譬如:时钟抖动、热噪声以及运放的一些限制参数(转换速率、有限DC增益、有限带宽等)。最后给出二阶低通ΣΔ调制器的模拟结果。     

中频带通ΣΔ调制器的建模与仿真设计

中频带通sigma-delta(ΣΔ)调制器是数字中频接收机的核心模块。基于一个双采样技术的低失真四阶带通sigma-delta调制器,分析了其主要的非理想特性,并建立了模型。利用根轨迹法对该调制器进行了稳定性研究,同时在TSMC 0.18μm的工艺下给出了该调制器的电路图以及版图的后仿真结果。后仿真结果显示了建立模型的准确性,证明该模型可以有效指导后级电路设计。     

Sigma-Delta调制器非理想特性建模

文章对三阶单环路结构的高阶sigma-delta A/D调制器的非理想特性,包括时钟抖动、MOS开关噪声、比较器迟滞性、放大器的输入噪声、单位增益带宽和有限直流增益等,进行了分析,提出了基于Matlab的高层次建模方法.通过系统仿真确定关键的电路参数和性能指标,在较高层次指导A/D转换器的电路结构级和晶体管级设计.     

基于Verilog-A的Sigma Delta系统行为级建模

介绍Verilog-A设计语言的特点,基于Sigma Delta系统介绍分级设计思想.分析开关电容型Sigma Delta调制器的非理想特性,主要包括时钟抖动、开关热噪声、运放增益、摆率等.在建立各自噪声模型的基础上,基于Verilog-A对二阶Sigma Delta系统行为级完整建模,通过仿真结果的比对,验证Verilog-A建模,总结其可准确预测指标并在一定程度上有效地削减仿真时间的优点.     

一种用于ADSL的高精度调制器的建模与仿真

要模数转换问题的研究中,介绍了∑-△调制器的过采样和噪声整形技术,为提高转换精度和速率,提出了一个采用四阶级联结构和∑-△调制技术实现高精度的调制器的行为级模型,根据影响建模的各种非理想因素,对各种实际非理想因素(例如开关热噪声、时钟抖动、运放的有限直流增益等)通过优化系统参数之后,可以得到一个用于ADSL设计中的高精度∑-△调制器行为级模型。并在MATLAB下对其仿真验证,结果表明为实际设计提供了依据。调制器在基带带宽1.5MHz、24倍过采样率条件下,系统的信噪比达到87dB,精确度可达14比特。     

六阶级联∑-△调制器的行为级建模

本文基于Matlab Simulink的环境下构建了一个3级6阶(2-2-2)的开关电容∑-△调制器的行为级模型,在考虑了非理想因素(包括时钟抖动、噪声、有限增益、有限带宽、压摆率、饱和电压等)的条件下,对其待性进行分析研究.仿真结果表明:该调制器在采样速率为51MHz时,信噪比为90dB,有效位数达到14bit.     

一种基于零点优化的低功耗ΣΔ调制器

设计了一种基于零点优化的低功耗ΣΔ调制器,该结构不需要传统ΣΔ调制器中的数字抵消逻辑部分,可以采用低增益的运算放大器(OTA),减小了设计难度。此外,设计的调制器中积分器的输出摆幅大大减小,积分器的非理想特性得到了抑制。通过优化零点位置,增加了调制器的稳定性和动态范围,信噪比和未进行零点优化相比得到了大大提高。设计的调制器采用0.35μm CMOS工艺仿真实现,仿真结果表明,在带宽为500 kHz、过采样为16 Mb/s时,信噪比达到90.9 dB,功耗仅为3.78 mW。     

Sigma-Delta微加速度计非理想因素建模与系统级设计

为了简化Sigma-Delta( ∑△)微加速度计接口电路晶体管级的仿真和优化,建立了系统中的非理想因素模型,并在此基础上完成了一种单环结构的∑△微加速度计的系统级设计.分析了敏感结构中固定极板运动、时钟抖动、开关热噪声、运算放大器噪声等非理想因素对系统的影响,并分别建立了Simulink模型.基于所建模型,设计了一种...     

两通道时间交织ΣΔ调制器研究及仿真

设计了一个二阶双通道时间交织ΣΔ调制器的系统结构并用SIMULINK对其进行系统仿真。阐明了此结构的设计理论依据及方法,同时从带宽和SNDR等方面与传统ΣΔ调制器进行了比较。     

高阶∑△ADC中积分器的设计

基于N阱0.6μm DPDM CMOS工艺,完成了高阶∑△ADC中第一级积分器的设计。分析了开关电容积分器的非理想特性,同时设计了一个对寄生电容不敏感的同相开关电容(SC)积分器,并特别采用旁路电容减小沟道电荷注入引起的谐波失真和噪声。在cadence下的电路仿真表明,积分器具有-104.9dB等效输入噪声;利用MATLAB进行系统仿真,∑△ADC的信号噪声畸变比(SNDR)达到100.5dB,满足系统16bit的要求。     

频率合成器中Σ-Δ调制器的设计与实现

本文首先介绍了Σ-Δ调制技术的基本原理,分析了一阶及高阶Σ-Δ调制器,最后结合一阶Σ-Δ调制器,给出了在FPGA器件上实现Σ-Δ调制器的设计。仿真结果表明,设计实现了Σ-Δ调制器,通过控制分频器实现了小数分频,方法简单易行。与运用Matlab软件仿真的结果完全一致,并进一步证实了高阶数字Σ-Δ调制对量化相位噪声的高通整形特性,从而有效地解决了小数分频频率合成器中的小数杂散问题,具有很高的实用性。     

Merging data converters and DSPs for mixed-signal processors

The use of sigma-delta conversion to produce high resolution without using analog components such as the precise resistors in an A/D (analog/digital) or a D/A (digital/analog) converter is reported. The use of sigma-delta technology solved the problem arising from the noise levels injected into the silicon substrate during digital switching (which limited the integration of both analog and digital circuitry on one VLSI chip) and allowed the implementation of the ADSP-21MSP50, the first mixed-signal processor. The basic elements of the converter are described, and its advantages and drawbacks as well as the implications for expanded DSP applications are examined. Included in the discussion are sampling and quantization noise, modulator design, frequency-domain analysis of the modulator, the use of digital filtering to minimize shaped-quantization noise, and the higher level of integration possible with this approach     

A novel, PLL-based frequency-to-digital conversion mechanism for sensor interfaces

Due to the ongoing trend towards smaller technologies, time-/frequency-to-digital conversion is gaining popularity. It benefits from the improved timing resolution in new technologies whereas voltage processing suffers from reduced signal swing and non-idealities. In this paper a new PLL architecture for digitization of sensor signals is described which fully exploits the benefits of frequency processing combined with the benefits from traditional sigma-delta voltage converters. Furthermore it is demonstrated that this architecture is flexible towards different sensor applications that require different specifications. Its working principle and relevance is explored with system-level simulations, and the robustness towards noise and non-idealities (temperature drift, voltage dependency) is demonstrated.     

一种反馈DAC优化技术

介绍了一种采用模拟电流自校正与数字加权平均(DWA)双重优化方法的电流舵DAC,在此基础上,根据文献设计了用于无线通讯的Sigma-Delta调制器,该调制器采用单环三阶结构,量化器采用4位9级量化器.在64MHz时钟频率,3.3V电源电压驱动下,Spectr仿真显示,采用该优化电流舵DAC的调制器达到79.6dB的信噪比和2MHz的信号带宽.与传统的单纯采用DWA和模拟校正技术的调制器进行比较,此调制器的信噪比比采用DWA技术提高68dB,比采用模拟校正技术提高16.3dB,同时比文献中的调制器提高7.6dB.从而说明,采用DWA和模拟校正混合优化技术改善反馈DAC的性能可进一步提高系统性能.     

A digital piezoelectric accelerometer with sigma-delta servo technique

This paper presents the design and performance of a direct digital accelerometer using oversampling sigma-delta servo electronics. The measuring system, also called an ‘electromechanical sigma-delta modulator’, is based on a piezoelectric measuring cell integrated inside the first stage of a second-order sigma-delta modulator. The piezoelectric measuring cell has a new structure in order to realize the acceleration sensing and the servo-loop summer. The active material used in an inexpensive and versatile piezoelectric polymer, polyvinylidene fluoride (PVDF). The accelerometer aims at a working range of ± 1 g and eight-bit resolution. It is suited for vibration measurement.     

一种新的连续时间Sigma-delta调制器系统设计方法

连续时间结构sigma-delta调制器中包括两种频域,是该结构设计的难点之一.本文在分析传统的连续时间调制器的设计流程后,提出一种新的设计方法.该方法增加了CT-DT变换,把连续时间环路滤波器转换到离散时间状态空间,利用离散时间调制器的成熟的设计平台进行设计,可以减少设计反复,加速设计收敛.利用该方法,本文设计了一个可用于手机电视的高速度、中高精度的连续时间sigma-delta调制器.     

级联结构的高阶∑-△调制器

介绍了∑-△调制器的转换原理。给出调制器的动态范围与阶数,过采样等因素的关系。提出了一种2-1级联∑-△调制器,整个电路达到三阶的效果,电路稳定。同时分析了由于系数不匹配和有限增益等因素对动态范围的影响。     

An approach for stability analysis of a single-bit high-order digital sigma-delta modulator

In this work we considered the stability of a single-bit high-order sigma-delta modulator under dc input. A new approach for stability analysis is proposed. A nonlinear circle map is suggested to model the dynamics of the modulator. An analogy between the dynamics of the sigma-delta modulator and the sinusoidal digital phase-locked loop (DPLL) is studied and an approximate fixed point solution is presented with stability criteria. Suggestions for designing stabilized high-order systems are presented.     

Simulink behavioral modeling of a 10-bit pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.