GaAs苛MESFET栅极漏电流退化机理分析

高温存储试验后某种ＧａＡｓ ＭＥＳＦＥＴ的栅－漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅－漏极低电压正向电流随温度的变化,定性估计了试验前后复合－产生中心浓度的变化,确定肖待基势垒触有源层的复合－产生中心浓度的增加是两种漏电流增大的原因,为高温下ＧａＡｓ ＭＥＳＦＥＴ的肖特基势垒接触存在栅金属下沉和扩散提供了证据．     

高频C—V法在肖特基势垒接触退化失效分析中的应用

ＧａＡｓ ＭＥＳＦＥＴ的栅极肖特基势垒接触退化的主要失效机理是栅金属下沉和栅金属扩散,因而引起有效沟道宽度减小或沟道掺杂浓度的下降。笔者用高频Ｃ－Ｖ法测定试验前后沟道载流子浓度随深度分布的变化,可获得栅金属下沉和栅金属扩散的信息,为肖特基接触退化的失效分析提供了一种有效的方法。     

Al／n—GaAs肖特基接触正向脉冲退化对GaAsIC的影响

本文描述了Ａｌ／ｎ－ＧａＡｓ肖特基接触的正向脉冲退化效应，探讨了当肖特基二极管承受正向电流冲击时，势垒高度ΦＢ升高，直接影响Ａｌ栅ＭＥＳＦＥＴｓ的特性，导致Ａｌ／ｎ－ＧａＡｓ ＩＣ失效的机理。     

GaAs MESFET中肖特基势垒接触退化机理的研究

本文对Ｔｉ／Ｍｏ／Ｔｉ／Ａｕ作为栅金属的ＧａＡｓＭＥＳＦＥＴ进行了四种不同的应力试验：１．高温反偏（ＨＴＲＢ）；２．高压反偏（ＨＲＢ）；３．高温正向大电流（ＨＦＧＣ）；４．高温存贮（ＨＴＳ）．通过ＨＲＢ，ΦＢ从０．６４ｅＶ减少到０．６２ｅＶ，理想因子ｎ略有增大．ＨＴＳ试验中ΦＢ从０．６７ｅＶ增加到０．６９ｅＶ．分析表明，这归因于界面氧化层的消失，以及Ｔｉ与ＧａＡｓ的反应；ＨＦＧＣ试验结果表明其主要的失效模式为烧毁，ＳＥＭ观察中有电徙动及断栅现象发生．ＡＥＳ分析表明。应力试验后的样品，肖特基势垒接触界面模糊     

高温正向大电流下TiAl,TiptAu栅GaAsMESFET的栅退化机理 …

针对ＧａＡｓＭＥＳＦＥＴ在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了ＴｉＡｌ栅和ＴｉＰｔＡｕ栅ＧａＡｓ ＭＥＳＦＥＴ的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的经是导致器件的跨导ｇｍ、栅反向漏电流Ｉｓ、夹断电压Ｖｐ等特性退化,甚至导致器件烧毁失效的主要原因。     

GaAs MESFET直流特性退化的失效分析

ＧａＡｓ ＭＥＳＦＥＴ直流特性退化的主要原因是源极漏极欧姆接触退化和栅极肖特基势垒接触退化，笔者用结构敏感参数电测法和Ｃ－Ｖ法进行失效定位和失效分析，为上述失效原因提供了证据。     

高温正向大电流下TiAl、TiPtAu栅GaAs MESFET的栅退化机理及其对器件特性的影响

针对ＧａＡｓ ＭＥＳＦＥＴ在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了Ｔｉａｌ栅和ＴｉＰｔＡｕ栅ＧａＡｓ ＭＥＳＦＥＴ的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的退化是导致器件的跨导ｇｍ、栅反向漏电流Ｉｓ、夹断电压Ｖｐ等特性退化,甚至导致器件烧毁失效的主要原因。     

GaAs双栅MESFET的PSPICE直流模型

提出了一种ＧａＡｓ双栅ＭＥＳＦＥＴ的ＰＳＰＩＣＥ直流模型．分析了ＧａＡｓ双栅ＭＥＳＦＥＴ漏极电流与两个控制栅偏置电压之间的关系,给出了漏极电流表达式．通过提取适当的模型参数,其直流输出特性的模拟曲线与实测曲线基本吻合,说明文中提出的ＧａＡｓ双栅ＭＥＳＦＥＴ的ＰＳＰＩＣＥ直流模型是有效的．     

全离子注入自对准难熔金属氮化物复合栅GaAs MESFET技术研究

本文研究了先进的全离子注入自对准难熔金属氮化物复合栅ＧａＡｓＭＥＳＦＥＴ场效应晶体管的工艺技术．首次使用Ｍｏ／ＺｒＮ作为复合栅的材料，ＡＩＮ薄膜作为器件介质钝化层，制作出了可用于ＧａＡｓ超高速集成电路的场效应晶体管，晶体管的跨导为１６０ｍＳ／ｍｍ，其栅漏反向击穿电压大于５Ｖ．     

硫钝化表面改善GaAs MESFET电特性

本文介绍了一种适用于ＧａＡｓ ＭＥＳＦＥＴ表面钝化的新方法。通过对器件进行硫钝化处理，我们发现钝化能使器件的击穿电压提高和表面漏电减少。我们认为造成这种现象的原因，是由于硫钝化减少了栅漏附近的ＧａＡｓ表面态密度。     

Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode

High-quality, ultrathin chemical vapor deposition (CVD) hafnium oxynitride (HfOxNy) gate dielectric with poly-silicon (Si) gate electrode has been investigated for the first time. This CVD HfOxNy gate dielectric film remains amorphous after 950 /spl deg/C N/sub 2/ annealing. Compared with HfO/sub 2/ films with poly-Si gate electrode and similar equivalent oxide thickness (EOT), CVD HfOxNy shows significantly reduction in leakage-current density and boron penetration and superior thermal and electrical stability.     

High temperature storage reliability of palladium coated copper wire in different EFO current settings

In recent years, palladium-coated copper (PdCu) wire has been widely used in microelectronic packaging. The electronic flame off (EFO) current setting will affect the distribution of palladium (Pd) during the free air ball (FAB) formation of PdCu wire. This study investigates the influence of EFO current settings on Pd distribution in the FAB and the bonded ball. The distribution and concentration of Pd is observed by using an electron probe micro analyzer (EPMA). Mechanical tests are used to evaluate the bond strength of the first bond. A high temperature storage test (HTST) is performed on the packaged IC at 200 °C for 500 h and 1000 h.The results indicate that different EFO current settings cause either complete or partial Pd coverage on FABs, which directly affects the Pd distribution at the bonded ball interface. The wire pull and ball shear tests show the bond strength decrease under three EFO current settings after HTST. This confirms that although Pd can serve as a protective layer for the bonded ball against attack from halides from within the epoxy molding compound (EMC), incomplete Pd coating and formation of the alloy may actually aggravate the corrosion on bonded ball.     

The formation of Ti-polycide gate structure with high thermalstability using chemical-mechanical polishing (CMP) planarizationtechnology

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi₂ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region     

Nonlinear characterization of GaN HEMT

DC I-V output, small signal and an extensive large signal characterization (load-pull measurements) of a GaN HEMT on a SiC substrate with different gate widths of 100μm and 1 mm have been carried out. From the small signal data, it has been found that the cutoff frequencies increase with gate width varying from 100μm to 1 mm, owing to the reduced contribution of the parasitic effect. The devices investigated with different gate widths are enough to work in the C band and X band. The large signal measurements include the load-pull measurements and power sweep measurements at the C band (5.5 GHz) and X band (8 GHz). When biasing the gate voltage in class AB and selecting the source impedance, the optimum load impedances seen from the device for output power and PAE were localized in the load-pull map. The results of a power sweep at an 8 GHz biased various drain voltage demonstrate that a GaN HEMT on a SiC substrate has good thermal conductivity and a high breakdown voltage, and the CW power density of 10.16 W/mm was obtained. From the results of the power sweep measurement at 5.5 GHz with different gate widths, the actual scaling rules and heat effect on the large periphery device were analyzed, although the effects are not serious.The measurement results and analyses prove that a GaN HEMT on a SiC substrate is an ideal candidate for high-power amplifier design.     

Electron irradiation of field-controlled thyristors

The influence of 3-MeV electron irradiation upon the characteristics of asymmetrical field-controlled thyristors has been examined for fluences of up to 16 Mrad. In addition to the lifetime reduction due to the radiation damage, carrier removal effects have also been observed in the very lightly doped n-base region of these devices. The leakage current, even after radiation at the highest fluenee, is not significantly increased and the blocking characteristies of these devices are not degraded. In fact, a small improvement in the blocking gain has been observed at low gate voltages. The electron irradiation has been found to increase the forward voltage drop during current conduction and to reduce the forced gate turn-off time. Gate turn-off times of less than 500 ns have been achieved by irradiation with a fluence of 16 Mrad. However, this is accompanied by a large increase in the forward voltage drop. Tradeoff curves between the forward voltage drop and the gate turn-off time have been obtained. From these curves, it has been determined that gate turnoff times of 1 µs can be obtained without a significant increase in the forward voltage drop for devices capable of blocking up to 600 V.     

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.     

Dual-polycide gate technology using regrowth amorphous-Si tosuppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 μm, and, as a result, 0.2 μm n-MOS/p-MOS spacing has been realized under an 850°C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p⁺ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current inthin-film SOI/NMOSFET's

The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.