Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A new single‐phase high‐power‐factor converter with buck and buck–boost hybrid operation

In recent years, a wide variety of high‐power‐factor converter schemes have been proposed to solve the harmonic problem. The schemes are based on conventional boost, buck, or buck–boost topology, and their performance, such as output voltage control range in the boost and buck topology or efficiency in the buck–boost topology, is limited. To solve this, the authors propose a single‐phase high‐power‐factor converter with a new topology obtained from a combination of buck and buck–boost topology. The power stage performs the buck and buck–boost operations by a compact single‐stage converter circuit while the simple controller/modulator appropriately controls the alternation of the buck and buck–boost operation and maintains a high‐quality input current during both the buck and buck–boost operations. The proposed scheme results in a high‐performance rectifier with no limitation of output voltage control range and a high efficiency. In this paper, the principle and operation of the proposed converter scheme are described in detail and the theory is confirmed through experimental results obtained from 2‐kW prototype converter. © 2000 Scripta Technica, Electr Eng Jpn, 131(3): 91–100, 2000     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

An 11‐μ W, 9‐bit fully differential,cyclic/algorithmic ADC in 0.13 μm CMOS

This paper describes a fully differential, cyclic, analogue‐to‐digital converter (ADC). It utilizes a 4‐bit binary weighted capacitor array to obtain 9‐bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew‐rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13 μm CMOS process and occupies 650 × 850μm² active area. At 10 kS/s sampling rate, the ADC consumes 11 μW. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage (V _{D C}  = 1.5 V, V _{A C}  = 200mV _pp, f  = 1 kHz). The measured peak of differential nonlinearity and integral nonlinearity is  + 0.26/ − 0.67 and  + 0.65/ − 0.59, respectively. At 250 Hz, effective number of bit is 8.4 bits, S F D R  = 66.7 dB and S N D R  = 52.6 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Multiple‐model adaptive robust dynamic surface control with estimator resetting

A multiple‐model adaptive robust dynamic surface control with estimator resetting is investigated for a class of semi‐strict feedback nonlinear systems in this paper. The transient performance is mainly considered. The multiple models are composed of fixed models, one adaptive model, and one identification model that can be obtained when the persistent exciting condition is satisfied. The transient performance of the final tracking system can be improved significantly by designing proper switching mechanism during the parameter tuning procedure. The semi‐globally uniformly ultimately bounded stability of the closed‐loop system can be easily achieved because of the framework of adaptive robust dynamic surface control. Numerical examples are provided to demonstrate the effectiveness of the proposed multiple‐model controller. Copyright © 2014 John Wiley & Sons, Ltd.     

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

Prescribed performance adaptive fuzzy dynamic surface control of nonaffine time‐varying delayed systems with unknown control directions and dead‐zone input

In this paper, an adaptive prescribed performance control method is presented for a class of uncertain strict feedback nonaffine nonlinear systems with the coupling effect of time‐varying delays, dead‐zone input, and unknown control directions. Owing to the universal approximation property, fuzzy logic systems are used to approximate the uncertain terms in the system. Since there is no systematic approach to determine the required upper bounds of errors in control systems, the prior selection of control parameters to have a satisfactory performance is somehow impossible. Therefore, the prescribed performance technique as a solution is applied in this study to bring satisfactory performance indices to the system such as overshoot and steady state performance within a predetermined bound. Dynamic surface control strategy is also introduced to the proposed control scheme to address the “explosion of complexity” behavior existing in conventional backstepping methods. To ease the control design, the mean‐value theorem is utilized to transform the nonaffine system into the affine one. Moreover, with the help of this theorem, the unknown dead‐zone nonlinearity is separated into the linear and nonlinear disturbance‐like bounded term. The proposed method relaxes a prior knowledge of control direction by employing Nussbaum‐type functions, and the effect of time‐varying delays are compensated by constructing the proper Lyapunov‐Krasovskii functions. The proposed controller guarantees that all the closed‐loop signals are semiglobally uniformly ultimately bounded and the error evolves within the decaying prescribed bounds. In the end, in order to demonstrate the superiority of this method, simulation examples are given.     

A universal‐input high‐power‐factor power supply without electrolytic capacitor for multiple lighting LED lamps

The AC–DC power supply for LED lighting application requires a long lifetime while maintaining high‐efficiency, high power factor and low cost. However, a typical design uses electrolytic capacitor as storage capacitor, which is not only bulky but also with short life span, thus hampering performance improvement of the entire LED lighting system. In this article, a SEPIC‐derived power factor correction topology is proposed as the first stage for driving multiple lighting LED lamps. Along with a relatively large voltage ripple allowable in a two‐stage design, the proposal of LED lamp driver is able to eliminate the electrolytic capacitor while maintaining high power factor and high efficiency. To further increase the efficiency of LED driver, we introduced and used the twin‐bus buck converter as the second‐stage current regulator with Pulse Width Modulation (PWM) dimming function. The basic operating principle and the deign consideration are discussed in detail. A 50‐W prototype has been built and tested to verify the proposal. Copyright © 2011 John Wiley & Sons, Ltd.     

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.     

Design and performance analysis of LMS algorithm based adaptive filter embedded with CFAR detector under non‐homogeneous clutter scenarios

The paper presents performance analysis of least‐mean‐square algorithm based adaptive filter embedded with constant false alarm rate (CFAR) detector for the purpose of better detection of target under non‐homogeneous clutter environment in radar application. The objective of this paper is to develop a method by redesigning the radar detector in such a way to emphasize the target response and de‐emphasize the clutter response. The hardware implementation using pipeline technique for the adaptive filter reveals its capability to support high sampling frequency, which is an ardent necessity for high performance radar. The moderate area‐delay‐product and low power consumption have made it suitable for hardware realization for such application. The extensive MATLAB simulation of proposed design shows remarkable improvement of detection performance in terms of signal‐to‐noise ratio of 17 dB considering probability of detection at 0.8 over the generic cell averaging CFAR (CA‐CFAR). Copyright © 2015 John Wiley & Sons, Ltd.     

A method for determining pseudo‐measurement state values for topology observability of state estimation in power systems

This paper proposes a new technique for determining state values in power systems. Recently, it has been useful for carrying out state estimation with PMU (Phasor Measurement Unit) data. The authors have developed a method for determining state values with an artificial neural network (ANN) considering topology observability in power systems. The ANN has the advantage of approximating nonlinear functions with high precision. The method evaluates pseudo‐measurement state values of data which are lost in power systems. The method has been successfully applied to the IEEE 14‐bus system. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 179(2): 27–34, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21235     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Multi‐voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire‐bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi‐voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time‐consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency. Copyright © 2015 John Wiley & Sons, Ltd.     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

A highly sensitive and ultra low‐power forward body biasing circuit to overcome severe process,voltage and temperature variations and extreme voltage scaling

Dynamic voltage scaling is one of the most popular methods used to reduce energy consumption in today's digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation‐sensitive and ultra low‐power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy‐delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post‐layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8‐bit pipelined Kogge–Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3 V and temperature changes of ?15 to 75 °C, the proposed technique brought about a seven times less delay variation, whereas energy‐delay product improved by 23% compared with a zero body biased adder. Copyright © 2013 John Wiley & Sons, Ltd.     

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.     

计及VSC和DFIG的电网动态无功优化模型

近年来,一系列特高压直流工程的投运和大型风电场等新能源的并网给特高压近区电网无功控制带来了新的挑战。为解决含柔性直流的交直流混联电网的无功优化控制问题,提出了含电压源换流器(Voltage Source Converter, VSC)并考虑双馈感应风机(Doubly-Fed Induction Generator, DFIG)无功支撑的动态无功优化模型。该模型以交直流电网全天网损最小为目标函数,约束包括交直流系统的潮流约束、直流变量的控制约束、离散控制变量动态调节次数约束及节点电压的安全约束。原模型是一个多时段非线性混合整数规划问题,缺乏快速有效的求解方法,通过线性化技术将原模型转化为能有效求解的二阶锥规划(Second Order Cone Programming, SOCP)问题。以IEEE30节点系统为例,通过仿真计算验证了所建模型和算法的有效性。