Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Analysis and implementation of a high‐efficiency zero‐voltage‐zero‐current‐switching DC–DC converter

A high‐efficiency zero‐voltage‐zero‐current‐switching DC–DC converter with ripple‐free input current is presented. In the presented converter, the ripple‐free boost cell provides ripple‐free input current and zero‐voltage switching of power switches. The resonant flyback cell provides zero‐voltage switching of power switches and zero‐current switching of the output diode. Also, it has a simple output stage. The proposed converter achieves high efficiency because of the reduction of the switching losses of the power switches and the output diode. Detailed analysis and design of the proposed converter are carried out. A prototype of the proposed converter is developed and its experimental results are presented for validation. Copyright © 2011 John Wiley & Sons, Ltd.     

Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

High‐efficiency current‐doubler rectifier with low output current ripple and high step‐down voltage ratio

This paper presents a current‐doubler rectifier with low output current ripple and high step‐down voltage ratio. In the proposed rectifier, two extra inductors are introduced to extend the duty ratio of the switches, which in turn reduces the peak current through the isolation transformer as well as the output current ripple; two extra diodes are used to provide discharge paths for the two extra inductors. To highlight the merits of the proposed rectifier, its performance indexes, such as voltage gain function, secondary winding peak current of the isolation transformer, and output current ripple, are analyzed and compared with the conventional current‐doubler rectifier. In this paper, a zero‐voltage‐switching phase‐shift full‐bridge converter with the proposed rectifier with an input voltage of 400 V, output voltage of 12 V, and full load power of 500 W has been implemented and verified, and experimental results have shown that 90% conversion efficiency could be achieved at full load. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Output current ripple reduction of LED driver using ceramic‐capacitor‐input circuit and buck‐boost converter

This article proposes an LED driver that consists of a ceramic‐capacitor‐input rectifier and a buck‐boost converter. The LED driver has an advantage of long life because it does not contain any electrolytic capacitors. However, the issue with electrolytic capacitor‐less LED driver is that the ripple of the smoothed voltage becomes large due to insufficient capacitance of the smoothing capacitor. The proposed method, which uses the discontinuous current mode of a buck‐boost converter, reduces the output current ripple under such conditions. Experimental results using a 5.7 W LED driver prototype demonstrate that the proposed method reduces the output current ripple and that the percent flicker becomes 4.4%, which is smaller than the recommended upper limit of 8%.     

A high step‐up half‐bridge DC/DC converter with a special coupled inductor for input current ripple cancelation and extended voltage doubler circuit for power conditioning of fuel cell systems

This paper presents a high step‐up soft switched dc–dc converter having the feature of current ripple cancelation in the input stage that is specialized for power conditioning of fuel cell systems. The converter comprises a special half‐bridge converter and a rectifier stage based upon the voltage‐doubler circuit, in which the coupled‐inductor technology is amalgamated with switched‐capacitor circuit. The input current with no ripple is the principal characteristics of this topology that is achieved by utilizing a small coupled inductor. In addition, the low clamped voltage stress across both power switches and output diodes is another advantage of the proposed converter, which allows employing the metal–oxide–semiconductor field‐effect transistors with minuscule on‐state resistance and diodes with lower forward voltage‐drop, and thereby, the semiconductors' conduction losses diminish considerably. The inherent nature of this topology handles the switching scheme based on the asymmetrical pulse width modulation in order for switches to establish the zero voltage switching, leading to lower switching losses. Besides, because of the absence of the reverse‐recovery phenomenon, all diodes turn off with zero current switching. At last, a 250‐W laboratory prototype with the input voltage 24 V and output voltage 380 V is implemented to verify the especial features of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd. Copyright © 2015 John Wiley & Sons, Ltd.     

A single‐stage phase‐shifted full‐bridge AC/DC converter with variable frequency control

This letter presents a single‐stage soft‐switched full‐bridge AC/DC converter for low‐voltage/high‐current output applications. A phase‐shifted method with a variable frequency control is used to regulate the DC bus voltage and the output voltage of the single‐stage AC/DC converter. The proposed circuit topology and control scheme exhibit superior performances (i.e. high power factor, high‐efficiency, and ring‐free features). Correspondingly, a laboratory prototype, 500 W 5V/100A AC/DC converter, is implemented to verify the feasibility of the proposed design. Copyright © 2009 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Dimmable integrated CMOS LED driver based on a resonant DC/DC hybrid‐switched capacitor converter

This paper presents a 7.7 ‐ mm² on‐chip LED driver based on a DC/DC resonant hybrid‐switched capacitor converter operating in the MHz range with and without output capacitor. The converter operation allows continuously dimming the LED while keeping control on both peak and average current. Also, it features no flickering even in the absence of output capacitor and for light dimmed down to 10% of the nominal value. The capacitors and switches of the LED driver are integrated on a single IC die fabricated in a low‐cost 5 V 0.18‐μm bulk CMOS technology. This LED driver uses a small (0.7 mm²) inductor of 100 nH, which is 10 times smaller value than prior art integrated inductive LED drivers, still showing a competitive peak efficiency of 93% and achieving a power density of 0.26 W/mm² (0.34 W/mm³).     

A ZVS‐ZCS phase shift full bridge DC‐DC converter with secondary‐side control for battery charging applications

The output power requirement of battery charging circuits can vary in a wide range, hence making the use of conventional phase shift full bridge DC‐DC converters infeasible because of poor light load efficiency. In this paper, a new ZVS‐ZCS phase shift full bridge topology with secondary‐side active control has been presented for battery charging applications. The proposed circuit uses 2 extra switches in series with the secondary‐side rectifier diodes, operating with phase shift PWM. With the assistance of transformer's magnetizing inductance, the proposed converter maintains zero voltage switching (ZVS) of the primary‐side switches over the entire load range. The secondary‐side switches regulate the output voltage/current and perform zero current switching (ZCS) independent of the amount of load current. The proposed converter exhibits a significantly better light load efficiency as compared with the conventional phase shift full bridge DC‐DC converter. The performance of the proposed converter has been analyzed on a 1‐kW hardware prototype, and experimental results have been included.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

A soft‐switching high step‐up DC‐DC converter with a single magnetic component

A soft‐switching high step‐up DC‐DC converter with a single magnetic component is presented in this paper. The proposed converter can provide high voltage gain with a relatively low turn ratio of a transformer. Voltage doubler structure is selected for the output stage. Due to this structure, the voltage gain can be increased, and the voltage stresses of output diodes are clamped as the output voltage. Moreover, the output diode currents are controlled by a leakage inductance of a transformer, and the reverse‐recovery loss of the output diodes is significantly reduced. Two power switches in the proposed converter can operate with soft‐switching due to the reflected secondary current. The voltages across the power switches are confined to the clamping capacitor voltage. Steady‐state analysis, simulation, and experimental results for the proposed converter are presented to validate the feasibility and the performance of the proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

Step‐up/step‐down DC‐DC converter with near zero input/output current ripples

A novel single switch two diode wide conversion ratio step down/up converter is presented. The proposed converter is derived from the conventional single‐ended primary inductor converter (SEPIC) topology, and it can operate as a capacitor‐diode voltage multiplier, which offers simple structure, reduced electromagnetic interference (EMI), and reduced semiconductor voltage stress. The main advantages of the proposed converter are the continuous input/output current, higher voltage conversion ratio, and near‐zero input and output current ripples compared with the conventional SEPIC converter. The absence of both a transformer and an extreme duty cycle permits the proposed converter to operate at high switching frequencies. Hence, the overall advantages will be: higher efficiency, reduced size and weight, simpler structure and control. The theoretical analysis results obtained with the proposed structure are compared with the conventional SEPIC topology. The performance of the proposed converter is verified through computer simulations and experimental results. Copyright © 2012 John Wiley & Sons, Ltd.     

An interleaved high step‐up DC‐DC converter with double boost paths

This paper proposed a novel high step‐up converter with double boost paths. The circuit uses two switches and one double‐path voltage multiplier cell to own the double boost and interleaved effects simultaneously. The voltage gain ratio of the proposed DC‐DC converter can be three times the ratio of the conventional boost converter such that the voltage stress of the switch can be lower. The high step‐up performance is in accordance with only one double‐path voltage multiplier cell. Therefore, the number of diodes and capacitors in the proposed converter can be reduced. Furthermore, the interleaved property of the proposed circuit can reduce the losses in the rectifier diode and capacitor. The prototype circuit with 24‐V input voltage, 250‐V output voltage, and 150‐W output power is experimentally realized to verify the validity and effectiveness of the proposed converter. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis and implementation of a power management unit with a multiratio switched capacitor DC–DC converter for a supercapacitor power supply

An energy‐harvesting system requires an energy‐storing device to store the energy retrieved from the surrounding environment. Rechargeable batteries are commonly used to store this energy; however, because of the limited number of charge/discharge cycles, they need to be periodically replaced. A supercapacitor, which has, ideally, a limitless number of charge/discharge cycles, avoids this problem. In this case, it is required for the power management unit to produce a constant output voltage as the supercapacitor discharges. This paper presents a system with a multiratio switched capacitor DC–DC converter, in a 130‐nm technology, with a maximum output power of 2 mW, a maximum efficiency of 79.63% and a maximum output ripple, in the steady state, of 23 mV for an input voltage range of 2.3–0.87 V. The proposed converter has four operation states, to maximize its efficiency, that correspond to the conversion ratios of 1/2, 2/3, 1/1 and 3/2. Its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use two asynchronous time machines to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system were verified by using electrical simulations. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel quasi‐Z‐source indirect matrix converter

A new type of three‐phase quasi‐Z‐source indirect matrix converter (QZS‐IMC) is proposed in this paper. It uses a unique impedance network for achieving voltage‐boost capability and making the input current in continuous conduction mode (CCM) to eliminate the input filter. The complete modulation strategy is proposed to operate the QZS‐IMC. Meanwhile, a closed‐loop DC‐link peak voltage control strategy is proposed, and the DC‐link peak voltage is estimated by measuring both the input and capacitor voltages. With this proposed technique, a high‐performance output voltage control can be achieved with an excellent transient performance even if there are input voltage and load current variations. The controller is designed by using the small‐signal model. Vector control scheme of the induction motor is combined with the QZS‐IMC to achieve the motor drive. A QZS‐IMC prototype is built in laboratory, and experimental results verify the operating principle and theoretical analysis of the proposed converter. The simulation tests of QZS‐IMC based inductor motor drive are carried out to validate the proposed converter's application in motor drive. Copyright © 2013 John Wiley & Sons, Ltd.     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

Hybrid DC–DC converter with high efficiency,wide ZVS range,and less output inductance

In this paper, a new soft switching direct current (DC)–DC converter with low circulating current, wide zero voltage switching range, and reduced output inductor is presented for electric vehicle or plug‐in hybrid electric vehicle battery charger application. The proposed high‐frequency link DC–DC converter includes two resonant circuits and one full‐bridge phase‐shift pulse‐width modulation circuit with shared power switches in leading and lagging legs. Series resonant converters are operated at fixed switching frequency to extend the zero voltage switching range of power switches. Passive snubber circuit using one clamp capacitor and two rectifier diodes at the secondary side is adopted to reduce the primary current of full‐bridge converter to zero during the freewheeling interval. Hence, the circulating current on the primary side is eliminated in the proposed converter. In the same time, the voltage across the output inductor is also decreased so that the output inductance can be reduced compared with the output inductance in conventional full‐bridge converter. Finally, experiments are presented for a 1.33‐kW prototype circuit converting 380 V input to an output voltage of 300–420 V/3.5 A for battery charger applications. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.