Multivariate theory‐based passivity criteria for linear fractional networks

In traditional linear network theory, the positive‐real (PR) criteria are widely used to judge the passivity of elements and networks in the light of the fact that there exists an equivalent relationship between the passivity and the PR property of their immittance functions (matrices). However, the equivalence will no longer hold when the fractional elements are introduced into the network, and the PR criteria are not suitable in complex frequency domain anymore. On the other hand, the rapid development of fractional‐order circuits and systems and the corresponding study in fractional circuit analysis and designs put forward an urgent requirement for the passivity criterion, which can tackle linear fractional networks. Hence, in this paper, we propose new passivity criteria for linear fractional networks by aid of generalized Tellegen's theorem and multivariable PR theory. By using the proposed criteria, the passivity of linear fractional networks can be judged, and the steps of the proposed criterion are illustrated by examples.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

Multiple operating points in a square‐root domain first‐order filter

In this paper novel corrective circuits to avoid multiple operating points in a square‐root domain first‐order filter are proposed. By employing a DC test it is demonstrated that the filter possesses three operating points (two stable and one unstable) and the corrective circuits enforce the proper operating mode. The corrective circuits and filter are able to operate with very low supply voltages (as low as V_GS+2V_DSsat). Moreover, a detailed analysis concerning the impact that produces the corrective circuits on the filter performance is discussed. Both measurement and simulation results are provided to validate the circuits and analysis employed. Copyright © 2006 John Wiley & Sons, Ltd.     

Design equations for fractional‐order sinusoidal oscillators: Four practical circuit examples

Four practical sinusoidal oscillators are studied in the general form where fractional‐order energy storage elements are considered. A fractional‐order element is one whose complex impedance is given by Z = a(jω)^±α, where a is a constant and α is not necessarily an integer. As a result, these oscillators are described by sets of fractional‐order differential equations. The integer‐order oscillation condition and oscillation frequency formulae are verified as special cases. Numerical and PSpice simulation results are given. Experimental results are also reported for a selected Wien‐bridge oscillator. Copyright © 2007 John Wiley & Sons, Ltd.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

Time‐domain properties of reactive dual circuits

The present work explores some effects of the replacement of capacitors by inductors and vice versa in state and semistate models of lumped circuits. Such a replacement, when performed together with an inversion of the capacitance and inductance matrices, yields a transformation of the form λ→λ^?1 in the system spectra. In the semistate context, this covers in particular extremal cases in which null eigenvalues or infinite ones with higher index appear in the matrix pencil associated with the model; these cases describe certain pathological circuit configurations. This approach leads to a discussion of new properties of strictly passive circuits; specifically, from the known fact that the index of strictly passive circuits does not exceed two, we derive that the index of null eigenvalues in this setting cannot exceed one. This precludes in particular Takens‐Bogdanov degeneracies, defined by an index‐two double‐zero eigenvalue, in strictly passive circuits. Although the results are addressed in a linear context, they can be extended via linearization to non‐linear problems, as it is the case in the transformation of singularity‐induced bifurcation phenomena into steady bifurcations discussed at the end of the paper. Copyright © 2006 John Wiley & Sons, Ltd.     

Design for testability of high‐order OTA‐C filters

A study of oscillation‐based test for high‐order Operational Transconductance Amplifier‐C (OTA‐C) filters is presented. The method is based on partition of a high‐order filter into second‐order filter functions. The opening Q‐loop and adding positive feedback techniques are developed to convert the second‐order filter section into a quadrature oscillator. These techniques are based on an open‐loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth‐order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth‐order cascade, inverse follow‐the‐leader feedback (IFLF) and LF OTA‐C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation‐based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA‐C filters, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

Adaptive synchronization of fractional‐order complex networks via pinning control

Adaptive synchronization of a class of fractional‐order complex networks is investigated in this paper. On the basis of the fractional‐order system stability theory, adaptive synchronization criteria of fractional‐order complex networks with 0 < q < 1 is achieved. Furthermore, pinning control method is then suggested to control the networks, and adaptive strategy is employed to tune the control gains and coupling strength. Because the nodes with high degree may not be the center of the networks, a new attempt to choose the pinned nodes on the basis of the closeness centrality scheme is proposed. Finally, numerical simulations are given to verify the effectiveness of the proposed approach based on the closeness centrality scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

An algorithm for direct identification of passive transfer matrices with positive real fractions via convex programming

The paper presents a new algorithm for the identification of a positive real rational transfer matrix of a multi‐input–multi‐output system from frequency domain data samples. It is based on the combination of least‐squares pole identification by the Vector Fitting algorithm and residue identification based on frequency‐independent passivity constraints by convex programming. Such an approach enables the identification of a priori guaranteed passive lumped models, so avoids the passivity check and subsequent (perturbative) passivity enforcement as required by most of the other available algorithms. As a case study, the algorithm is successfully applied to the macro‐modeling of a twisted cable pair, and the results compared with a passive identification performed with an algorithm based on quadratic programming (QPpassive), highlighting the advantages of the proposed formulation. Copyright © 2010 John Wiley & Sons, Ltd.     

Experimental studies on realization of fractional inductors and fractional‐order bandpass filters

This paper presents the hardware realization and performance study of fractional inductors of order 0 < α < 2. The fractional inductors used in this work have been realized with the help of general impedance converter circuit and fractional capacitors. Impedance characterization of fractional inductors with different exponents has been carried out experimentally. Also a generalized approach to design a fractional‐order bandpass filter is discussed in this work. The fractional‐order bandpass filter consists of a series combination of a resistor, a fractional inductor of order 1 < α < 2, and a fractional capacitor of order 0 < β < 1. The performance of fractional‐order bandpass filters has been studied and compared with corresponding integer‐order filters through both experimentation and simulation. Copyright © 2014 John Wiley & Sons, Ltd.     

Magnetic properties of Pr‐Fe‐Co‐V‐W‐Si‐B system exchange spring magnets

The melt‐spun ribbons of Pr‐Fe‐Co‐V‐W‐Si‐B system alloys were prepared by single roller rapid‐quenching method. The effects of composition, surface velocity, and heat treatment on the magnetic properties were investigated. The P₉sFe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 alloy ribbons prepared at a surface velocity of 12.5 m/s were crystallized by heat treatment, and the optimum heat‐treatment condition was found to be at 575°C for 3 min, for which the magnetic properties were (BH)_max = 136.1 kJ/m³, J_r = 0.93 T, H_cJ = 652.2 kA/m, and H_cB = 528.3 kA/m. The temperature coefficients of J_r and H_cJ for the ribbons crystallized from melt‐spun ribbons of Pr₉Fe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 alloy were α(J_r)_ave = ?0.057%/°C and α(H_cJ) = ?0.450%/°C. The value of (B)_max for the compression molding Pr₉Fe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 isotropic bonded magnet prepared by using the ribbons annealed at 575°C for 3 min is 80.0 kJ/m³, and the density is 6.24 Mg/m³. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(3): 10–16, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20211 Copyright © 2006 Wiley Periodicals, Inc.     

Energy model based loss‐minimized speed control of induction motor with a full‐order observer

In this paper, a loss‐minimization algorithm is developed to achieve maximum efficiency in terms of slip frequency. The optimal value of slip frequency can be obtained by minimizing all controllable losses of the induction motor (IM). The ratio of magnetic energy converted to torque (W_T) to magnetic energy stored in the rotating field (W_q) is defined in terms of slip frequency to obtain an error function that is used to design a controller to achieve the desired speed. Since the energy model of the IM can be expressed by the multi‐input and multi‐output (MIMO) system, an MIMO optimal regulator is proposed to achieve the desired speed with maximum efficiency. To design an optimal regulator, it is necessary to measure all state quantities. But W_T and W_q cannot be measured directly. Therefore, a full‐order observer is proposed to estimate these state quantities. The gains of the observer system are calculated by using the pole placement technique. Consequently, the observer system becomes stable. The performance of the proposed controller and observer system are verified by using simulation. With regard to the simulation results, it can be concluded that the desired speed can be achieved by using the proposed controller and the unknown state quantities can be estimated properly by using the proposed observer system. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A DC stabilized log‐domain nth‐order multifunction filter based on the decomposition of nth‐order HP filter function to FLF topology

The design of high‐order log‐domain filters can be easily accomplished by transposing already known linear‐domain G_m‐C filter topologies to their counterparts in the log‐domain through the employment of a set of complementary operators. To achieve the G_m‐C filter topologies, the multiple feedback approach is widely used due to its accrued advantages. In this paper a synthesis approach for the development of an nth‐order multifunction log‐domain filter comprising lowpass (LP), highpass (HP) and bandpass (BP) filter functions is proposed. The approach is based on the decomposition of nth‐order HP filter function to follow‐the‐leader‐feedback (FLF) topology. The design is simple and simultaneously achieves nearly all of the chief advantages. The design offers superior performance factors vis‐à‐vis the ones recently reported. To verify the high‐order behavior of the topology, a 5th‐order multifunction filter was designed and the achieved simulated results verify the theory. Copyright © 2008 John Wiley & Sons, Ltd.     

An oscillatory noise‐shaped quantizer for time‐based continuous‐time sigma‐delta modulators

In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

Electrical circuits RC,LC, and RL described by Atangana–Baleanu fractional derivatives

In this paper, the analytical solutions for the electrical series circuits RC, LC, and RL using novel fractional derivatives of type Atangana–Baleanu with non‐singular and nonlocal kernel in Liouville–Caputo and Riemann–Liouville sense were obtained. The fractional equations in the time domain are considered derivatives in the range α ∈(0;1]; analytical solutions are presented considering different source terms introduced in the fractional equation. We solved analytically the fractional equation using the properties of Laplace transform operator together with the convolution theorem. On the basis of the Mittag–Leffler function, new behaviors for the voltage and current were obtained; the classical cases are recovered when α =1. Copyright © 2017 John Wiley & Sons, Ltd.     

Optimal design of lattice wave digital fractional‐order Butterworth filter

This letter presents the design of digital fractional‐order Butterworth filter (DFOBF) of order (n+α) , where n is an integer, and α ∈ (0,1) , from the perspective of optimal realization. The magnitude–frequency characteristic of the DFOBF is optimally modeled using the computationally efficient lattice wave digital filters (LWDFs). Design examples for the third‐ and fifth‐order LWDF‐DFOBFs with various values of n, α_, and cut‐off frequencies are presented.