A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

High‐efficiency grid‐connected inverter topology for low‐power photovoltaic applications

For low‐power applications, such as household photovoltaic panels, the efficiency and reliability of the distributed generation system is an important issue. A high‐efficiency inverter topology derived from the normal full‐bridge circuit is proposed for grid‐connected photovoltaic applications. In the proposed topology, a couple of diodes are added in parallel with the grid‐frequency switches as freewheeling diodes working during the positive and negative half‐cycles of the utility voltage, respectively, thus preventing the output current from flowing through the body diodes of switches. Because of its natural configuration, simple operation, and three‐level function, the proposed topology features a high level of efficiency and reliability over a wide voltage range, and allows the best cost–effective ratio. These characteristics are compared with those of other existing advanced topologies, followed by a theoretical analysis on the output filter and the implemented circuit of modulation scheme. Experimental results from a 3 kW hardware prototype verify the feasibility of the proposed solution. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

A power‐efficient current‐mode neural/muscular stimulator design for peripheral nerve prosthesis

This paper presents a 16‐channel power‐efficient neural/muscular stimulation integrated circuit for peripheral nerve prosthesis. First, the theoretical analysis is presented to show the power efficiency optimization in a stimulator. Moreover, a continuous‐time, biphasic exponential‐current‐waveform generation circuit is designed based on Taylor series approximation and implemented in the proposed stimulation chip to optimize the power efficiency. In the 16‐channel stimulator chip design, each channel of the stimulator consists of a current copier, an exponential current generator, an active charge‐balancing circuit, and a 24‐V output stage. Stimulation amplitude, pulse width, and frequency can be set and adjusted through an external field‐programmable gate array by sending serial commands. Finally, the proposed stimulator chip has been fabricated in a 0.18‐μm advanced complementary metal‐oxide‐semiconductor process with 24‐V laterally diffused metal oxide semiconductor option. The maximum stimulation power efficiency of 95.9% is achieved at the output stage with an electrode model of 10‐kΩ resistance and 100‐nF capacitance. Animal experiment results further demonstrate the power efficiency improvement and effectiveness of the stimulator.     

基于GaN HEMT的半桥LLC优化设计和损耗分析

较之于传统硅器件,新出现的增强型氮化镓晶体管GaN HEMTs(gallium nitride high electron mobility transistors)具有很高的开关速度和高功率密度的特性,可以为直流变换器提供有效的改进。为了解决GaN HEMT在硬开关应用场合下的波形振荡并提高功率密度和效率,采用半桥LLC谐振变换器为本次应用的拓扑结构。以减小损耗为目的,优化了LLC的谐振参数和死区时间。在400 V输入电压、开关频率300 kHz和输出电压18 V电流12 A的测试条件下,效率达到95.59%。最后对变换器的损耗来源进行分析,损耗的理论计算值接近实际测量值,证明了方法具有一定的实用性。     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab . The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, I_d‐V_gs, I_d‐V_ds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Theoretical studies of the capacitance‐voltage characteristics of metal‐ferroelectric‐GaN structures

We have simulated the capacitance versus voltage characteristics (C‐V) of metal‐ferroelectric‐gallium nitride (GaN metal‐ferroelectric‐semiconductor) structures and found useful design rules for improving the devices' performance. The thickness effects of ferroelectric film on the C‐V are studied. When the ferroelectric Pb(Zr, Ti)O3 thickness is no more than 100 nm, the GaN metal‐ferroelectric‐semiconductor structures can approach inversion just under 5 V, which is the generally applied voltage used in semiconductor‐based integrated circuits. This marked improvement of C‐V behaviors is mainly due to the high dielectric constant and large polarization of the ferroelectric gate oxide. Copyright © 2011 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

A novel low‐loss control strategy for bidirectional DC–DC converter

Bidirectional DC–DC converter with phase‐shift control is commonly used for hybrid electric vehicle and fuel‐cell vehicle applications. This converter is characterized by simple circuit topology and soft‐switching implementation without additional devices. Despite these advantages, the efficiency is poor at light load condition because of high switching and conduction losses caused by high RMS inductor current. To achieve zero‐voltage switching (ZVS) for all power MOSFETs, a constant offset inductor current is maintained to conduct the antiparallel body diodes before MOSFETs turn on. A control strategy of combining duty ratio and phase‐shift modulation is proposed to reach the constant offset current. By reaching the constant offset current, the RMS inductor current can be reduced significantly, and ZVS can be achieved in all load variation ranges, resulting in high efficiency. A 2.5‐kW prototype is implemented to verify the control scheme, and a minimum efficiency of 97.3% is achieved at light load condition. Copyright © 2017 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A high‐speed MIMO FFT processor with full hardware utilization

The conventional way to design multi‐input‐multi‐output (MIMO) fast Fourier transform (FFT) processors for MIMO‐orthogonal frequency division multiplexing systems is to adopt a parallel architecture which uses as many single‐input‐single‐output FFT processors as the number of transmit/receive antennas. These MIMO FFT processors can provide high throughput, but they perform with low hardware utilization when there are not all input sequences available. In this paper, we propose a high‐speed MIMO FFT processor which can work efficiently with high throughput and full hardware utilization for variable 1 to 4 input sequences. Our MIMO FFT processor is designed by reordering and distributing data sequences to all data paths and is constructed by some novel modules. Being synthesized by using UMC 0.18‐μm process demonstrates that our 64‐point 4 × 4 FFT can achieve high throughput with full hardware utilization and perform correctly up to 62.25 MHz with low power consumption for variable 1 to 4 input sequences.     

A single‐stage LED streetlight driver with PFC and digital PWM dimming capability

This paper proposes a single‐stage light‐emitting diode (LED) driver that offers power‐factor correction and digital pulse–width modulation (PWM) dimming capability for streetlight applications. The presented LED streetlight driver integrates an alternating current–direct current (AC–DC) converter with coupled inductors and a half‐bridge‐type LLC DC–DC resonant converter into a single‐stage circuit topology. The sub‐circuit of the AC–DC converter with coupled inductors is designed to be operated in discontinuous‐conduction mode for achieving input‐current shaping. Zero‐voltage switching of two active power switches and zero‐current switching of two output‐rectifier diodes in the presented LED driver decrease the switching losses; thus, the circuit efficiency is increased. A prototype driver for powering a 144‐W‐rated LED streetlight module with input utility‐line voltages ranging from 100 to 120 V is implemented and tested. The proposed streetlight driver features cost‐effectiveness, high circuit efficiency, high power factor, low levels of input‐current harmonics, and a digital PWM dimming capability ranging from 20% to 100% output rated LED power, which is fulfilled by a micro‐controller. Satisfying experimental results, including dimming tests, verify the feasibility of the proposed LED streetlight driver. Copyright © 2016 John Wiley & Sons, Ltd.     

An extensible two‐phase high voltage‐boosting converter with automatic current balance

In this study, an extensible 2‐phase interleaved high step‐up converter with automatic current balance is presented. This converter uses coupled inductors and energy‐transferring capacitors to improve the voltage gain of the traditional 2‐phase interleaved boost converter as well as employs these energy transferring capacitors to do automatic current balance. Furthermore, the voltage gain can be enhanced not only by adjusting the turns ratio but also by increasing the numbers of phases, diodes, and energy‐transferring capacitors. Therefore, it can be used in high input current and high step‐up voltage applications. In this paper, the basic operating principles of the proposed converter are described and analyzed, and finally, its effectiveness is demonstrated by experiment. In addition, the field‐programmable gate array, named EP13T100C8N and manufactured by Altera Co, is used as a control kernel, and an experimental prototype, with input voltage of 12 V, output voltage of 200 V, and rated output power of 200 W, is given to provide the effectiveness of the proposed converter.     

Two‐switch flyback PWM DC‐DC converter in continuous‐conduction mode

The two‐switch flyback DC‐DC converter is an extended version of the conventional single‐switch flyback converter. An additional switch and two clamping diodes serve as a simple, but an effective way to limit the switch overvoltages, which occur in the conventional single‐switch flyback converter due to the ringing of the resonant circuit formed by the transformer leakage inductance and the transistor output capacitance. The clamping diodes in the two‐switch flyback topology clamp the maximum voltage across each switch equal to the DC input voltage. This paper presents a detailed steady‐state analysis and design procedure of the diode‐clamped two‐switch flyback converter operated in continuous‐conduction mode (CCM). The power loss in each component of the two‐switch flyback converter is compared with those of the single‐switch flyback converters with and without RCD clamp, and is presented in a tabular form. The two‐switch flyback converter was bread‐boarded to validate the theoretical analysis. Experimental results from a 10 V/30 W, 100 kHz laboratory prototype verified that the maximum switch voltage is limited to the DC input voltage. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel single‐stage AC–DC converter with quasi‐resonant zero‐voltage‐switching for high power factor and high efficient applications

A new single‐stage‐isolated ac–dc converter that can guarantee both high efficiency and high power factor is proposed. It is based on a new dc–dc topology that has prominent conversion ratio similar to that of boost topology so that it is adequate to deal with the universal ac input. In addition, since it utilizes the transformer more than others based on the general flyback topology, the size of whole power system can be reduced due to the reduced transformer. Moreover, the voltage stresses on the secondary rectifiers can be clamped to the output voltage by adopting the capacitive output filter and clamp diode, and the turn‐off loss in the main switch can be reduced by utilizing the resonance. Furthermore, since this converter operates at the boundary conduction mode, the line input current can be shaped as the waveform of a line voltage automatically and the quasi‐resonant zero‐voltage switching can be obtained. Consequently, it features higher efficiency, lower voltage stress, and smaller sized transformer than other topologies. A 100 W prototype has been built and tested as the validation of the proposed topology. Copyright © 2010 John Wiley & Sons, Ltd.