Performance characterization of a microwave transistor subject to the noise and matching requirements

In this paper, the gain G_T of a microwave transistor is expressed analytically in terms of the mismatchings (V_in ≥ 1, V_out ≥ 1) at the ports, noise figure F ≥ F_min and the [z]‐parameter and noise parameters. Firstly, because the input termination Z_S determines the noise F ≥ F_min, thus the input termination Z_S is pre‐determined to lie on the tangent constant noise and available gain circles so that the maximum power delivery is ensured for the given noise. Then, a design configuration is constructed in the input impedance Z_in‐ plane covering the gain and the required input and output mismatch circles within the Unconditionally Stable Working Area for the predetermined input termination Z_S. Finally, the compatible (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadrates for either required or optimum (V_in ≥ 1, V_out ≥ 1) couples are obtained with their (Z_S, Z_L) couples from the analysis of the design configuration. Furthermore, a case study is also presented for the full flexible performance characterization of a selected microwave transistor. It can be concluded that the near future microwave transistor is expected to be identified by performance data base built by its compatible (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadrates and the (Z_S, Z_L) terminations within the device operation domain to overview all the possible low‐noise amplifier designs using the full device capacity. Copyright © 2015 John Wiley & Sons, Ltd.     

A simple and efficient honey bee mating optimization approach to performance characterization of a microwave transistor for the maximum power delivery and required noise

In this work, a simple, efficient and multi objective Honey Bee Mating Optimization (HBMO) is presented for the performance characterization of a microwave transistor to deliver maximum power to the load with the required noise F_req. Thus all the possible compatible {F_req ≥ F_min, V_out = 1, G_Tmax} triplets and the corresponding source Z_S and load Z_L = Z^*_out (Z_S) terminations can be obtained in the device operation domain of (V_DS, I_DS and f) without working analytically for the nonlinear performance and stability equations. HBMO is a recently emerging meta‐heuristic algorithm that combines the powers of the simulated annealing and genetic algorithms. Here, a microwave transistor is chosen as a case study, effectiveness and efficiency of the HBMO are shown by comparing its performance to those of the standard meta‐heuristics Genetic and Particle Swarm algorithms and the mean cost results for 10 runs are found to be 0.22, 1.65 and 1.85, respectively, for the comparable execution times. Furthermore, all the numerical results are found to agree with their analytical counterparts obtained using the microwave, linear circuit and noise theories. The Feasible Design Target Space FDTS can be built by the cross relations among all the possible compatible {F_req ≥ F_min, V_out = 1, G_Tmax} triplets together their terminations {Z_S, Z_L = Z^*_out (Z_S)} covering all the possible amplifier designs where both noise figure and output power are at a premium. Copyright © 2015 John Wiley & Sons, Ltd.     

Full flexible performance characterization of a feedback applied transistor with LNA applications

In this paper, the full flexible performance characterization of a transistor with series inductive/parallel capacitive feedback is carried out in terms of LNA applications. For this purpose, the input VSWR V_in–maximum available gain G_Tmax variations are constructed for a high technology low-noise transistor that is subject to the required noise figure F_req(f) ≥ F_min(f) along the device's operation band depending on the feedback. These V_in–G_Tmax variations result in the application of a design chart that indicates which value of feedback can be applied within which region of the operation band with the improvable trade-off between the V_in and output VSWR V_out for the Freq(f) ≥ Fmin(f). Following this, the optimum trade-off between V_in and V_out is made for the necessary operation frequency regions using the load impedance Z_L as an instrument with the predetermined source impedance Z_S. Finally, the LNA applications of a series inductive/parallel capacitive feedback applied transistor with the optimum V_in, V_out, and G_T subject to Freq(f) ≥ Fmin(f) ≥ are also presented as distributed across the entire bandwidth in the different operation bands. It can be concluded that this rigorous work will enable a designer to utilize the entire operation frequency band of transistor through using only a single series inductive/parallel capacitive feedback for the LNA designs of Freq(f) ≥ Fmin(f) with the optimum trade-offs among its performance measures.     

Design of ultra low‐power RF oscillators based on the inversion coefficient methodology using BSIM6 model

This paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient (IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade‐off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross‐coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

Mapping of circuit variables into two‐port network variables in basic amplifier structures: identifying new topologies

In this paper, we report on a unique observation which enables the unification of the analysis for different amplifier structures. In particular, we report that the change from one type of amplifier to the other can be understood via a mapping of source‐load circuit variables (V_s, R_s, I_i, I_o, I_L, V_o) into two‐port network variables (V₁, V₂, I₁, I₂). As such, unified expressions for (A_v,Z_i,A_i,Z_o) are derived. Further, a Matlab code is written to search for all valid mappings out of 3⁸ different possibilities. Copyright © 2013 John Wiley & Sons, Ltd.     

Multiple operating points in a square‐root domain first‐order filter

In this paper novel corrective circuits to avoid multiple operating points in a square‐root domain first‐order filter are proposed. By employing a DC test it is demonstrated that the filter possesses three operating points (two stable and one unstable) and the corrective circuits enforce the proper operating mode. The corrective circuits and filter are able to operate with very low supply voltages (as low as V_GS+2V_DSsat). Moreover, a detailed analysis concerning the impact that produces the corrective circuits on the filter performance is discussed. Both measurement and simulation results are provided to validate the circuits and analysis employed. Copyright © 2006 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and optimization of a novel biasing for constant‐gain CMOS open‐loop amplifiers

A replica biasing circuit is presented which allows open‐loop gain in CMOS amplifiers to be accurately set. The proposed solution is a new biasing which takes advantage of a triode‐biased transistor instead of the ΔV_GS approach which is the traditional one. The circuit can be applied to both RF and IF amplifiers which are based on resistive loads in order to achieve high‐frequency and/or low‐noise performance. A detailed analysis of second‐order effects is then given which emphasizes the effects due to mobility degradation, channel‐length modulation and threshold voltage mismatches. Simulated results show a good sensitivity to process variations. Copyright © 2001 John Wiley & Sons, Ltd.     

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the I_ON/I_OFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, S_Vth (the V_th sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a S_Vth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

     

A TCAD approach for non-linear evaluation of microwave power transistor and its experimental verification by LDMOS

A simulation technique is developed in TCAD to study the non-linear behavior of RF power transistor. The technique is based on semiconductor transport equations to swot up the overall non-linearity’s occurring in RF power transistor. Computational load-pull simulation technique (CLP) developed in our group, is further extended to study the non-linear effects inside the transistor structure by conventional two-tone RF signals, and initial simulations were done in time domain. The technique is helpful to detect, understand the phenomena and its mechanism which can be resolved and improve the transistor performance. By this technique, the third order intermodulation distortion (IMD₃) was observed at different power levels. The technique was successfully implemented on a laterally-diffused field effect transistor (LDMOS). The value of IMD₃ obtained is −22 dBc at 1-dB compression point (P _{1 dB}) while at 10 dB back off the value increases to −36 dBc. Simulation results were experimentally verified by fabricating a power amplifier with the similar LDMOS transistor.     

Design, fabrication and characterization of dual-channel real space transfer transistor

In this paper, using a δ-doping dual-channel structure and GaAs substrate, a real space transfer transistor (RSTT) is designed and fabricated successfully. It has the standard Λ-shaped negative resistance I–V characteristics as well as a level and smooth valley region that the conventional RSTT has. The negative resistance parameters can be varied by changing gate voltage (V _GS). For example, the PVCR varies from 2.1 to 10.6 while V _GS changes from 0.6 V to 1.0 V. The transconductance for I _P (ΔI _P/ΔV _GS) is 0.3 mS. The parameters of V _P, V _V and threshold gate voltage (V _T) for negative resistance characteristics arising are all smaller than the value reported in the literature. Therefore, this device is suitable for low dissipation power application. __________ Translated from Journal of Semiconductors, 2008, 29(1): 136–139 [译自: 半导体学报]     

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V_DD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V_DD and BLB is discharged to the ground. The proposed non‐V_DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

An accurate and simplified small signal parameter extraction method for GaN HEMT

In this paper, development of a small signal model for 2 × 200 μm GaN HEMT based on the conventional 20-element model is presented. The proposed model presents a direct parameter extraction algorithm, instead of the hybrid optimization approach, that provides simplification, accuracy, and less computational complexity. The extrinsic elements are extracted using a modified cold pinch-off condition while discarding the unwanted forward biasing of the gate. The negative drain to source capacitance C_ds is also observed in the ohmic region (for smaller V_DS). An excellent agreement found between the measured and modeled data for a wide range of frequencies and bias values shows the effectiveness of the proposed approach. The proposed modeling technique is validated with a good agreement between the achieved bias dependency of intrinsic parameter values and the respective theoretical parameter values.     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

Implementing extra element theorem using nullor approach

This letter presents a method of implementing the extra element theorem (EET) on the computer by using the nullor method. The EET involves the calculation of two driving‐point impedances (dpi's), namely the conventional dpi, Z_d, and the null dpi, Z_n. The proposed method is used mainly for calculating Z_n. The method is simplified by representing any given circuit using exclusively RC‐nullor and R‐nullor equivalent circuits, thereby permitting the use of a single (parallel) version of the EET. The proposed method is applied to the linearized boost converter model to derive the fragmented version of the duty‐ratio‐to‐output transfer function. Copyright © 1999 John Wiley & Sons, Ltd.     

Imaging lung function using rapid dynamic acquisition of <Emphasis Type="Italic">T</Emphasis><Subscript>1</Subscript>-maps during oxygen enhancement

This paper describes imaging of lung function with oxygen-enhanced MRI using dynamically acquired T ₁ parameter maps, which allows an accurate, quantitative assessment of time constants of T ₁-enhancement and therefore lung function. Eight healthy volunteers were examined on a 1.5-T whole-body scanner. Lung T ₁-maps based on an IR Snapshot FLASH technique (TE = 1.4 ms, TR = 3.5 ms, FA = 7 ^∘) were dynamically acquired from each subject. Without waiting for full relaxation between subsequent acquisition of T ₁-maps, one T ₁-map was acquired every 6.7 s. For comparison, all subjects underwent a standard pulmonary function test (PFT). Oxygen wash-in and wash-out time course curves of T ₁ relaxation rate (R ₁)-enhancement were obtained and time constants of oxygen wash-in (w _in) and wash-out (w _out) were calculated. Averaged over the whole right lung, the mean w _out was 43.90 ± 10.47 s and the mean (w _in) was 51.20 ± 15.53 s, thus about 17% higher in magnitude. Wash-in time constants correlated strongly with forced expired volume in one second in percentage of the vital capacity (FEV₁ % VC) and with maximum expiratory flow at 25% vital capacity (MEF25), whereas wash-out time constants showed only weak correlation. Using oxygen-enhanced rapid dynamic acquisition of T ₁-maps, time course curves of R ₁-enhancement can be obtained. With w _in and w _out two new parameters for assessing lung function are available. Therefore, the proposed method has the potential to provide regional information of pulmonary function in various lung diseases.     

Figures‐of‐merit genetic extraction for InGaAs lasers,SiGe low‐noise amplifiers,and ZnSe/Ge/GaAs HBTs

In this paper, we have successfully developed an intellectual parameter‐extraction methodology on the basis of a genetic algorithm (GA), involving the efficient search‐space separation and local‐minima‐convergence prevention schemes. Via an evolutionary simulation tool complemented with appropriate analytic equations, the enhanced approach has been applied to determine the significant figures‐of‐merit (FoMs), including internal quantum efficiency (η_i) as well as transparency current density (J_tr) of semiconductor lasers, minimum noise figure (NF_min) as well as associated available gain (G_A,assoc) of low‐noise amplifiers (LNAs), and DC as well as AC characteristics of heterojunction bipolar transistors (HBTs). For the first time, demonstrated FoM‐extraction results, which coincide well with the actually measured data, for state‐of‐the‐art InGaAs quantum‐well lasers, advanced SiGe LNAs, and abrupt ZnSe/Ge/GaAs HBTs are simultaneously presented to validate this multi‐parameter analysis and robust optimization. Copyright © 2011 John Wiley & Sons, Ltd.     

Loss analysis based on constant gate current for MOSFET selection of CCM boost converter

Predicting the power losses in a semiconductor is an essential design process to determine the converter's size. In the continuous conduction mode (CCM) boost converter, the power loss of MOSFETs can be divided into the loss not depending on the gate current (the conduction loss) and losses depending on the gate current (the switching losses) leading to I_DS transition period and V_DS transition period. Therefore, analysis of both conduction and switching losses based on constant gate current can realize the MOSFET selection to improve the efficiency of the CCM boost converter.