Quartz-resonator inductance

The impedance of a quartz-crystal AT-plate resonator is shown to be a function of the efficiency of energy trapping in the resonator. Expressions for resonator inductance in terms of the electrode dimensions, plateback and resonance frequency are derived for a common type of resonator design.     

Mutator realized inductance

A physical realization using only operational amplifiers and discrete passives presented for the type one LR mutator is used to obtain grounded and floating inductances of 5 H and Q values greater than 10 for frequencies to 10 kHz.     

Modeling of magnetizing inductance and leakage inductance in amatrix transformer

Winding and core geometries are described for a matrix transformer constructed from integrated core and z-folded flex circuits. The magnetizing inductance is derived using the reluctance method and exploiting structural periodicity and symmetry. The internal leakage inductance is computed from the magnetic field distribution, and the interconnect leakage inductance from inductance formulas and current distribution. The results show that the interconnects are responsible for most of the leakage inductance. The modeling predicts inductance values that agree well with experimental measurements     

Smallest p-n-p-n memory cell

Although the p-n-p-n device is suitable for a 1-bit/cell static mamory, it has not yet been put to practical use because of its large cell size. By employing a sophisticated process involving single-crystal/poly-Si simultaneous growth on the same substrate, the smallest-sized vertical p-n-p-n device has been developed. Using this cell structure, a 12-bit scanner with 21.2-MHz transfer frequency, 16-µm pitch and 10-µmW/bit power dissipation has been fabricated. This cell structure is also applied to a static RAM with 22 × 27 = 594 µm²cell size. A high switching speed as well as a high packing density is predicted by this configuration.     

Soft-error-immune switched-load-resistor memory cell

A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p^--substrate are completely shielded by n⁺-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10⁵ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell     

The twin-port memory cell

A novel full-CMOS six-transistor memory cell that provides uncontested and overlapped two-port read accesses to one-cell, and concurrent READ/WRITE operations to separate cells, has been designed and functional test circuits is fabricated. This twin-port cell is based on the traditional cross-coupled inverter, but with a versatile access scheme. Balanced differential access transistors have given way to independent and complementary access transistors attached to a common readout node in the cell. Independent N-port and P-port word lines control the NMOS and PMOS access devices routing stored data to N and P bit lines, respectively. Each port has the potential of accessing a cell without interference from activities at other port even if addressing the same cell. This cell, with a complementary single bit line and access transistor per port structure, is only 11% larger than a similarly constructed conventional six-transistor single-port CMOS cell.     

Bipolar dynamic memory cell

A bipolar dynamic memory cell for use in a high-speed random- access memory consists of a cross-coupled pair of transistors and two diodes. Information is dynamically stored using a bistable charge distribution and must be refreshed at a frequency of 1 kHz by a SELECT operation. Standby power per memory cell is in the nanowatt range. The cell requires only 3 interconnect lines and can be fabricated with standard bipolar technology on 12-mil/SUP 2/ silicon area. Cycle time is limited by the speed of decoding, driving, and sensing circuits and is estimated to be 50 ns for a 512-bit RAM chip with complete on-chip decoding.     

有互感的电感耦合介观电路的量子化及其量子效应

利用拉格朗日函数给出了有互感的电感耦合介观电路体系的哈密顿量,通过引入一幺正算符使体系哈密顿算符对角化,然后借助IWOP技术,求出了幺正算符的正规乘积形式;同时还讨论了电路体系中电荷及其共轭量的量子涨落.结果发现,利用该电路体系可以产生转动的两单模压缩真空态.     

High-frequency on-chip inductance model

The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that the random signal lines as well as designated ground lines provide return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like propagation mode is observed above 10 GHz, revealing a unique relationship between capacitance and inductance of the signal line. Incorporating the random capacitive coupling effect, our frequency-dependent RLC model is confirmed to be valid up to 100 GHz.     

非线性电感的测量

对非线性电感的测量及其物理机制进行深入的研究,通过一种新型实验,分析了非线性电感的测量结果和电感理论及磁介质理论的联系。对于电子产品中带有铁芯的电感元器件的试验具有一定的指导意义。     

Small-size low-power bipolar memory cell

A d.c.-stable random-access memory cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2/spl times/3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil/SUP 2/. The cells have been operated at an extremely low d.c. standby power of less than 0.1 /spl mu/W/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.     

Regulated cascode switched-current memory cell

A new sampled-current signal processing cell is presented. When operated with its memory transistor in saturation it can be designed with high signal swing and low supply voltage. Alternatively, with the addition of a simple clock circuit to produce nearly constant switch charge injection, the memory transistor may be operated in nonsaturation to improve accuracy.<>     

SDW MOSFET static memory cell

The single device well (SDW) memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells and thus a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 /spl mu/m technology, an SDW memory cell consumes an area of 600 /spl mu/m/SUP 2/ and has an average power consumption of 10 /spl mu/W at 5 V supply. Another version of the cell using a polyresistor is also discussed.     

A high-performance SI memory cell

In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to a high accuracy cell with measured errors less than 200 ppm for input currents between 50 and 85 μA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies     

Inexact match associative memory cell

A new associative memory cell is described and analysed using SPICE3d1. The CMOS cell uses current summation to compute, in parallel, Hamming distances between the search key and each word in the memory. For 32 bit words, SPICE simulations of a 2 mu m process show a delay of 4 ns/bit for Hamming distances less than three.<>     

A hot-hole erasable memory cell

Electrical erasure of in-system memory chips has always been a desire for circuit operation. A novel technique which utilizes hot-hole injection in the snapback regime for memory erasure is described. This operation does not require a high-cost quartz lid or a special device structure. Although endurance characteristics are limited by channel hot-carrier-induced degradation, hundreds of WRITE and ERASE cycles can be easily achieved.     

On-chip inductance cons and pros

Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed.     

Oscillating circuit using nonlinear inductance

An oscillating circuit with nonlinear inductance is examined. A general characteristic of an inductance is used. Using the method of Samoilo, expressions for the oscillation frequency, the current harmonics, the characteristics of the forced oscillations and the characteristics of the parametric resonance are obtained, without limitations on the oscillation amplitude.     

Electronically tunable floating inductance simulator

In this letter, a new floating inductance simulator circuit is presented. The proposed structure consists of only one grounded capacitor without any external resistors and two different active elements. The active elements are dual-output current-controlled current conveyor (DO-CCCII) and operational transconductance amplifier (OTA). The proposed inductance simulator can be tuned electronically by changing the biasing current of the DO-CCCIIs or by changing the current of the OTA. Moreover, the circuit does not require any conditions of component matching. It has a good sensitivity performance with respect to tracking errors. As an application, the proposed inductance simulator is used to construct a fourth-order resistively terminated LC band-pass filter. The theoretical analysis is verified by the SPICE simulation results.     

Short antenna with active inductance

It has been found that integration of an active inductance with a short antenna gives higher antenna gains over a relatively wide frequency range. The gain of this system can be further improved by integrating a suitable wideband amplifier with it.