Unusually abrupt switching in submicrometer thin-film transistorsusing a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 μm or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

采用不同透明电极的非晶铟镓锌氧化物薄膜晶体管

采用透明材料ITO和AZO为源漏电极,在室温下利用射频磁控溅射方法制作了底栅结构的非晶铟镓锌氧化物薄膜晶体管。实验发现,制备的薄膜晶体管均表现出了良好的开关特性。其中采用AZO为电极的薄膜晶体管的场效应迁移率为1.95cm2/V.s,开关比为4.53×105,在正向偏压应力测试下,阈值电压的漂移量为4.49V。     

Low-frequency noise in low temperature unhydrogenated polysilicon thin film transistors

Low-frequency noise measurements are performed in two types of low temperature polysilicon thin film transistors (TFTs). For the first TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility fluctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the fluctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite different from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering.     

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension. With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.      

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively.These laser crystallized TFT's show poorer reliability properties than solid-phase crystallized TFT's. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations.Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV_T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFT's by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFT's where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).     

Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer

The investigations on the device instabilities of amorphous InGaZnO thin film transistors (a-IGZO TFTs) with ITO local conducting buried layer (LCBL) under the source/drain region and in the middle of the active channel region have been performed under negative bias and illumination stress. From the increased drain current of a-IGZO with ITO LCBL, one can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length. The reason for the less degradation of a-IGZO TFTs with LCBL under negative bias stress than that of device without LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradation of a-IGZO with ITO LCBL under negative bias and illumination stress was more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination.     

High-performance thin-film transistors in large grain sizepolysilicon deposited by thermal decomposition of disilane

The characteristics of polycrystalline silicon thin-film transistors (TFTs), fabricated on films deposited in an LPCVD system using disilane, were investigated as a function of grain size. The grain size and its statistical distribution were correlated with processing conditions; optimum conditions to maximize grain size for device applications were determined. The dependence of the ON current and the OFF (leakage) current of polysilicon TFTs, as well as of their statistical distributions, on the grain size, the gate dielectric processing temperature, the channel length, and the device structure are reported and discussed. Larger grain size polycrystalline silicon films were found to yield devices with higher mobilities and lower leakage currents. TFTs, fabricated in polysilicon films with average grain sizes of 1.8 μm with thermally grown silicon dioxide as gate dielectric, had ON/OFF current ratio well above 10⁸, average effective mobility value of 170 cm²/V.s and subthreshold slope of 0.3 V/dec     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

A new MOSFET structure with self-aligned polysilicon source and drain electrodes

A new MOSFET structure whose source and drain electrodes are self-aligned to the gate electrode is proposed. The new structure utilizes a second layer of polysilicon which is defined by a preferrential etching to form the source and drain regions. Due to the self-alignment property of the source and drain regions, the total device size is decreased by about 50 percent over the conventional MOS transistors when the same design rule is used. Experimental results of the new structure are presented.     

Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors

Air gap thin-film transistors (TFTs) were fabricated using a solid phase crystallization process. Undoped polycrystalline silicon (polysilicon) was used as the active layer and a highly doped polysilicon bridge was used as the gate, which promotes the air gap. These TFTs have comparable threshold voltage (V/sub T/) and subthreshold slope characteristics to TFTs fabricated using pulsed laser crystallization, and using silicon dioxide as gate insulator. The low value of V/sub T/ is very important for low power consumption. Moreover, the air-gap TFT fabrication process is compatible with low-temperature glass substrate technology, which allows the integration of sensors and electronics circuits.     

Reliability of amorphous InGaZnO TFTs with ITO local conducting buried layer for BEOL power transistors

The device reliability of a-IGZOTFTs with ITO local conducting buried layer (LCBL) has been investigated under positive gate bias stress and hot carrier stress for the application as BEOL power transistors. The drive current of a-IGZO TFTs could be controlled by the modulation of ITO LCBL thickness and distance under source/drain electrode. The threshold voltage shifts, the drain current degradation, and breakdown voltage have been measured and discussed according to the different ITO LCBL thickness and distance. The devices with thick ITO and short ITO distance are desirable for a power device for High/Low type I/O bridges. The devices with thin ITO and long ITO distance are desirable for Low/High type I/O bridges. The breakdown voltages are decreased with the increase of ITO thickness.     

Fabrication of SOS MOSFETs using two-step doping with excimer laser

Using two-step doping with excimer laser, p-channel MOSFETs were fabricated in thin silicon films on sapphire (SOS). Source and drain p ⁺ layers were formed using two-step doping with only one melting pulse of excimer laser. Devices were processed at room temperature except for the LPCVD gate oxide deposition at 450°C. High-quality thin film transistors (TFTs) were fabricated with on/off current ratio of 7 and a field effect hole mobility of 145 cm²/V s     

Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region

This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large voltage drop across the source and drain junctions.      

Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.