Low temperature glass-to-glass wafer bonding

In this paper, results of successful anodic bonding between glass wafers at low temperature are reported. Prior to bonding, a special technique was used, i.e., an amorphous and hydrogen free silicon film was deposited on one of the glass wafers using a sputtering technique. The effects of bonding temperature and voltage were investigated. The bonding temperature and the voltage applied ranged from 200/spl deg/C to 300/spl deg/C and 200 V to 1000 V, respectively. As the bonding temperature and bonding voltage increased, both the unbonded area and the size of voids decreased. Scanning electron microscope (SEM) observations show that the two glass wafers are tightly bonded. The bond strength is higher than 10 MPa for all the bonding conditions. Furthermore, the bond strength increases with increasing bonding temperature and voltage. The study indicates that high temperature and voltage cause more Na/sup +/ ions to neutralize at the negative electrode, which leads to higher charge density inside the glass wafer. Furthermore, the transition period to the equilibrium state also becomes shorter. It is concluded that the anodic bonding mechanisms involve both oxidation of silicon film and the hydrogen bonding between hydroxyl groups.     

Germanium-on-insulator substrates by wafer bonding

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the final Ge film polish. The completed GOI substrate is characterized for film uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing.     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Development of reliable low temperature wafer level hermetic bonding using composite seal joint

A reliable composite metal seal comprising both intermetallic compounds (IMC) and solder joints, which are formed by transient liquid phase bonding and soldering respectively, is proposed and demonstrated in wafer level bonding experiments. Hermetic sealing is demonstrated on 8-in. wafers using low volume Cu/Sn materials at process temperatures as low as 280 °C. It is shown that the composite seal is stable when subjected to temperatures of 250 °C, and that it provides better hermeticity and reliability than an IMC seal alone.     

Germanium on sapphire by wafer bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10^?6 K^?1) and sapphire (5 × 10^?6 K^?1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm²/V s have been fabricated onto the thick germanium on sapphire layer.     

Microstructure examination of copper wafer bonding

The microstructure morphologies and oxide distribution of copper bonded wafers were examined by means of transmission electron microscopy (TEM) and energy dispersion spectrometer (EDS). Cu wafers exhibit good bond properties when wafer contact occurs at 400°C/4000 mbar for 30 min, followed by an anneal at 400°C for 30 min in N₂ ambient atmosphere. The distribution of different defects showed that the bonded layer became a homogeneous layer under these bonding conditions. The oxidation distribution in the bonded layer is uniform and sparse. Possible bonding mechanisms are discussed.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Bonding parameters of blanket copper wafer bonding

A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications. In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature, duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding condition for 3-D integration can be determined.     

铌酸锂晶片的键合减薄及热释电性能研究

铌酸锂(LN)作为一种热释电材料,可以被用于制作光电探测器敏感单元的敏感层,但通常LN晶片厚度为0.5 mm,远大于光电敏感单元厚度的要求,所以需要用键合减薄及抛光技术对LN晶片进行加工处理。本研究所用键合减薄技术主要包含:RZJ-304光刻胶键合、铣磨、抛光、剥离液剥离和丙酮清洗RZJ-304胶。利用该技术加工得到了面积为10 mm×10 mm,厚度为50μm,表面比较光滑,表面粗糙度为1.63 nm的LN晶片。LN晶片的热释电信号峰峰值在减薄抛光后为176 mV,是未经处理时的4倍,满足了热释电探测器敏感层的要求。     

Ultra CSP晶片级封装

取得专利的低成本小型封装随着市场对更小、更快和不太昂贵器件需要的增长，工业上正在寻找一种使产品从导线焊接封装转到直接进行芯片连接（DCA）的解决方案。在近几年间，芯片大小的封装（CSP）已经显现出在球栅阵列（BGA）和倒装片的空隙之间架起的桥梁。由于许多设计预先考虑向DCA转移，所以已经把倒装片引入到他们的CSP或BGA封装里了。Kulicke＆Soffa工业股份有限公司的K＆S倒装片分部已经超出了传统的封装和CSP封装的范围，而转到向Ultra CSP技术发展。这种UltraCSP技术是一种晶片级（Wafer Level）CSP方案，是利用一…     

Vertically coupled microring resonators using polymer wafer bonding

A new technique is presented to make vertically coupled semiconductor microring resonators that eases the fabrication process with devices more robust to ring-to-waveguide misalignments. Single-mode microring optical channel dropping filters are demonstrated for the first time in this configuration with Qs greater than 3000 and an on-resonance channel extinction greater than 12 dB. A 1×4 multiplexer/demultiplexer crossbar array with second-order microrings was also made and exhibited channel-to-channel crosstalk lower than 10 dB     

Heterogeneous silicon integration by ultra-high vacuum wafer bonding

Heterogeneous integration of technologically important materials, such as SiC/Si, GaN/Si, Ge/Si, Si/nano-Si/Si, SiC-on-insulator (SiCOI), and ZrO₂/SiO₂/Si, was successfully made by ultra-high vacuum (UHV) wafer bonding. A unique, UHV bonding unit, especially designed to control interface structure, chemistry, and crystallographic orientation within narrow limits, was used to produce homophase and heterophase planar interfaces. In-situ thin-film-deposition capability in conjunction with the wafer bonding offered even more flexibility for producing integrated artificial structures. Prebonding surface preparation was critically important for the formation of strong bonded interfaces. The substrate-surface morphology was examined by atomic-force microscopy (AFM) prior to bonding. In-situ Auger spectroscopy measurements of surface chemistry were invaluable predictors of bonding behaviors. Plasma processing very effectively cleaned the substrates, achieving a near-perfect interfacial bond at the atomic scale. The integrity of the bonded interfaces was studied in the light of their structural and chemical characteristics analyzed by high-resolution, analytical electron microscopy.     

Thin-film devices fabricated with benzocyclobutene adhesive wafer bonding

In this paper, we present and elaborate on die to wafer bonding technology with benzocyclobutene (BCB). This technology allows to fabricate a variety of reliable waferbonded components in a fairly simple way using only standard cleanroom equipment. We demonstrate the fabrication of passive devices such as microring resonators, as well as active components such as lasers and LEDs. We show good performance of these devices by presenting measurements of their characteristics. Furthermore, these devices were subjected to damp-heat testing, demonstrating the good quality of the BCB-bonding procedure. Finally, due to the low thermal conductivity of BCB, thermal management needs some attention. We present an analysis of the thermal problem and suggest a possible solution.     

Integrated GaAs Schottky mixers by spin-on-dielectric wafer bonding

A novel wafer bonding process has been used to integrate high quality GaAs devices on quartz substrates. The method of adhesion by spin-on-dielectric temperature enhanced reflow (MASTER) uses a spin-on-dielectric as a bonding agent to achieve a robust bond that in no way degrades either high frequency performance or reliability. A 585 GHz integrated mixer fabricated using this process has achieved record double-sideband mixer noise temperatures of 1,150 K at room temperature and 880 K at 77 K. Furthermore, the integrated mixers require no mechanical tuning, are easy to assemble, and repeatable. Precise control of the circuit geometry, coupled with the reduction of parasitic elements, allows greater accuracy of computer simulations and will therefore lead to better high frequency performance and bandwidth. This new technology is easily extended to other circuit designs and will allow the development of a new generation of submillimeter-wave integrated circuits     

Benzocyclobutene wafer bonding for III-V nanophotonic guiding structures

An adhesive wafer bonding technique for the fabrication of nanophotonic guiding structures, the design of which consists of a III-V semiconductor core buried in a polymer matrix, is reported. The bonding was realised owing to benzocyclobutene. Nanostructures are perfectly embedded in the void-free matrix to form high density photonic circuits.     

Overlap optimization in semiconductor waveguides by wafer bonding

In this work, we show that the use of a wafer-bonding technique, wherein an inverted half-waveguide structure is bonded on the upright half to form a complete waveguide, optimizes the overlap factor present in three-wave parametric interactions realized in 43m semiconductor waveguides. These optimized waveguides can be used for efficient frequency-mixing devices which detect or emit infrared light.     

Evaluation of wafer bonding and etch back for SOI technology

Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy (TEM), the critical processing parameters causing defect generation have been identified and the principal mechanisms of dislocation nucleation have been elucidated. Strain compensated bonded SOI wafers have also been evaluated by non-destructive elastic light scattering and optical beam induced current (OBIC) to obtain topographic defect maps of entire SOI wafers. This analytical technique has the capability to comprehensively characterize surface and subsurface morphological features which result from the bonding and thinning processing steps. A comparison of wafer bonding and etch back technology with different etch stop fabrication techniques is presented. In this review, it is demonstrated that the presence of a boron-doped etch stop layer, with its accompanying lattice contraction and strain compensation, represents a key difference in the observed morphological patterns of bonded SOI wafers.     

圆片级封装的研究进展

圆片级封装(wafer level package,WLP)因其在形状因数、电性能、低成本等方面的优势,近年来发展迅速。概述了WLP技术近几年的主要发展。首先回顾标准WLP结构,并从焊球结构等方面对其进行了可靠性分析。其次介绍了扩散式WLP工艺以及它的典型应用,并说明了扩散式WLP存在的一些可靠性问题。最后总结了WLP技术结合硅通孔技术(TSV)在三维叠层封装中的应用。     

MicroSMD-a wafer level chip scale package

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products