基于OTA的有源Gm-C复数带通滤波器的设计

设计了一种基于OTA的有源Gm-C复数带通滤波器,用以实现射频前端芯片中的中频滤波和镜像抑制功能,该滤波器采用Gyrator结构,将低通原型滤波器中的集总电感用有源电感进行替换,并依据复数变换理论,对浮地电容和接地电容进行复数变换,实现带通滤波器.滤波器中心频率为4.1 MHz,1 dB带宽2 MHz,带内增益13.27 dB,1.5倍带宽处抑制在40 dB以上,镜像抑制度40 dB.Gm-C滤波器集成度高,功耗低,适合于高频应用,是当前集成中频滤波器的热点.     

CMOS低中频有源复数带通滤波器设计

设计并实现了基于0.18 μm CMOS工艺的2.4 GHz无线传感网(Wireless Sensor Network)射频接收机低中频有源复数带通滤波器.该滤波器采用基于积分器单元的复数带通滤波器结构,同时实现镜像抑制和信号滤波的功能.仿真结果表明,复数带通滤波器的中心频率为2 MHz,通带带宽为2.4 MHz,通带电压增益约为12.5 dB,镜像抑制大于30 dB,相邻信道阻带衰减大于40 dB,噪声系数小于15 dB,消耗电流为5 mA.通过系统验证,本设计各项性能均满足无线传感网射频接收机的设计要求.     

低功耗Zigbee收发器镜像抑制滤波器设计

分析镜像抑制和带外衰减的要求,设计了适用于2.4 GHz Zigbee无线收发前端的镜像抑制滤波器.电路采用7阶巴特沃思OTA-C双二次结构.通过线性变换实现复数滤波.采用交叉耦合输入跨导器,扩大了输入线性范围.为减小滤波器频率偏差,设计了一种锁相环频率修调电路.电路利用0.18 μm CMOS工艺实现.测试结果表明,复数滤波器带宽2.54MHz,镜像抑制大于35 dB,偏移3.5 MHz抑制超过50 dB.在1.8 V电源电压下电流为0.86 mA.     

低功耗的巴特沃思复数滤波器设计

总结了复数域内的信号处理原理,并介绍了应用于GPS射频前端的低功耗巴特沃思复数滤波器设计实现.该滤波器工作电压为1.5 V,功耗小于1 mW.性能指标为:中心频率4 MHz,3 dB带宽为3 MHz,偏离中心频率1 MHz以内的通带纹波小于0.5 dB,镜像频率处的抑制比为70 dB以上.最后在0.18 μm工艺下实现版图面积为0.5×0.48 mm2.     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

三阶级联复数有源RC带通滤波器

采用0.18μmCMOS工艺设计了一款应用在无线传网中的三阶级联有源RC复数带通滤波器,同时设计了自动频率调谐电路(AFT)。该滤波器采用的是切比雪夫逼近函数予以实现。在5比特数字控制码开关电容阵列的控制下,AFT电路即可完成对主体滤波器电路频率变化的校正。仿真结果显示,滤波器的中心频率稳定在2MHz,通带带宽为2MHz,镜像抑制比大于34dB,相邻信道阻带衰减大于34dB,通带纹波小于1dB,消耗电流为2.3mA,工作电源电压为1.8V。     

移相型三厘米波段镜像抑制混频器

<正>镜像抑制混频器是通讯和其它电子系统中不可缺少的部件之一.一般达到镜像抑制的方法有两种,在混频器信号输入端设置带通滤波器(或带阻滤波器);另一种是在混频器设计中利用相位关系来区分中频输出是真正射频或镜频干扰信号,使有用中频信号输入到接收机,而镜像信号产生的干扰信号消耗或反射在匹配负载上.前者设计较简单,仅适用于高中频系统;但对工作频带较宽、频率捷变和低中频接收机系统就不适用.因此就只能采用后者,亦即移相型双平衡电路结构.     

C波段TVRO镜像频率抑制微带交指带通滤波器

微带交指带通滤波器具有结构紧凑、易于批量生产的特点，适用于ＴＶＲＯ超外差接收机中作为镜像频率抑制滤波器。本文给出有关设计公式、设计实例。     

QAM解调芯片中镜像抑制滤波器的VLSI实现

提出一种用于接收数字电视信号的QAM解调芯片中,初始解调电路的镜像抑制滤波器的VLSI实现方法,阐述了镜像抑制滤波器唧实现过程中所需要注意的问题。根据I,Q信号的特点,通过时分复用把两个低通镜像抑制滤波器合并为一个半带滤波器,来实现低通镜象抑制滤波器。     

GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

Waveguide Bandpass Filters for Millimeter-Wave Radiometers

A fundamental requirement for most mm-wave heterodyne receivers is the rejection of the input image signal which is located close to the local oscillator frequency. For this purpose we use a bandpass filter, which for heterodyne receivers is also called an image rejection filter. In this paper we present a systematic approach to the design of a waveguide bandpass filter with a passband from 100 to 110 GHz and upper rejection bandwidth in the range from 113 to 145 GHz. We consider two non-tunable filter configurations: the first one is relatively selective with 11 sections (poles) whereas the second one is simpler with 5 sections. We used established design equations to propose an initial guess for the geometries of the filters, optimized the geometries, constructed the filters using two different milling methods, measured their transmission and reflection characteristics, and compared the measurements with numerical simulations. Measurements of both filters agree well with simulations in frequency response and rejection bandwidth. The insertion loss of the 11-pole filter is better than 10 dB and that of the 5-pole filter is better than 5 dB. The 11-pole filter has a sharper attenuation roll-off compared with the 5-pole filter. The upper out-of-band rejection is better than 40 dB up to 145 GHz for the 11-pole filter and up to 155 GHz for the 5-pole filter.     

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-/spl mu/m bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm/sup 2/.     

多通道数字接收机的设计与实现

为了解决传统模拟中频接收机相位分辨率低等缺点,提出一种基于软件无线电的中频数字接收机技术。针对雷达信号的特点提出了脉宽匹配滤波器的设计方法。采用基于多相滤波的正交变换理论,以及基于脉宽匹配的数字滤波器方法完成了一种五通道中频数字接收机的设计。接收机利用五路高速A/D变换器对输入的模拟信号进行采样,然后将采样数据送入FPGA进行处理,最终完成了每两路信号相位差的提取。实验结果表明系统具有成本低、精度高、结构简单等特点,而且具有一定的工程应用价值。     

模拟中频滤波幅相特性对微波着陆相位信号解算的影响分析

在微波着陆机载接收机中,射频通道将 C 波段信号变换为中频信号,中频信号通过模拟中频滤波器送入到后级处理,模拟中频滤波器的幅相特性特别是相位特性的好坏对后级解算相位信息影响较大,合理的认识评价模拟中频滤波器特性对整机相位信号的影响,是设计与考核模拟中频滤波器的基础。本文介绍了微波着陆机载设备相位信号解算处理通路及原理,并从系统角度给出了模拟中频滤波器特性对与系统相位信号解算的影响,为模拟中频滤波器的设计及系统评价模拟滤波器的性能做出参考。     

18～40GHz超宽带小型化接收前端的仿真设计

研制了一种基于混合集成技术的18～40 GHz超宽带毫米波小型化接收前端,针对变频方案进行了设计,通过合理的频谱规划,使其能够满足系统要求。对宽带增益平坦度与镜像频率抑制2个指标实现进行了简要介绍,对关键的无源电路、增益均衡器与高抑制度带通滤波器进行了联合仿真设计,并通过详细的实际指标测试证实了仿真的准确性,提出了有效解决超宽带信道平坦度与高抑制度的实现方法。     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

中频信号接收与处理电路研究

介绍了一种中频信号接收与处理电路设计,在研究了中频信号带通采样理论的基础上,设计了一种基于ADC+FPGA+DSP结构框架的中频信号接收与处理电路,对ADC转换器电路、FPGA及外围电路、DSP及其外围电路以及电源模块电路的设计进行了详细介绍。该中频信号接收与处理电路可以实现125MSPS的采样速率,FPGA和DSP的采用为后续信号处理提供了强大的硬件支持。因此,该中频信号接收与处理电路具有较高的实用价值。     

强干扰情况下用于CDMA系统的时空域联合处理

本文提出了一个时空域联合处理技术来对抗码分多址通信系统中的多址干扰.它由智能天线和多用户联合检测结合而成,智能天线可以压制与有用信号来向不同的干扰,余下的与用户信号来向相同的干扰可以被多用户联合检测系统消除.这种结构在干扰严重的信道仍能得到令人满意的效果.     

Photonic bandpass filters with high skirt selectivity and stopband attenuation

A new photonic signal processor topology that simultaneously achieves both a high-Q and a high skirt selectivity and stopband attenuation filter response is presented. It is based on a novel dual-cavity bandpass optical structure in which two pairs of active fiber Bragg grating cavities are used with an optical gain offset to control the poles and stopband attenuation characteristics of the filter. This concept enables a large improvement in the filter stopband attenuation, rejection bandwidth, and skirt selectivity to be realized. Measured results demonstrate both a narrow bandpass bandwidth of 0.4% of center frequency and a skirt selectivity factor of 16.6 for 40 dB rejection, which corresponds to a 6.5-fold improvement in comparison to conventional single cavity high-Q structures. To our knowledge, this is the best skirt selectivity reported for a photonic bandpass filter to date. The new photonic filter structure has been experimentally verified and excellent agreement between measured and predicted responses is shown.