RImCom: Raster-order Image Compressor for Embedded Video Applications

This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom offers up to 3x compression that is either lossless or lossy at very reasonable PSNR values. The 180 nm ASIC implementation of RImCom achieves 28 fps at Ultra-HD resolution in the slow corner of synthesis. RImCom can match the fps of the state-of-the-art in the literature with 20 % less area or can achieve twice the fps with 55 % more area. Our FPGA implementation is the only end-to-end FPGA solution in the literature to achieve to this day over 60 fps at Full-HD resolution and to offer rate control. This work was motivated by video processing applications that require the previous frame(s) besides the current frame. When processing HD video streams, even when only one previous frame is required besides the current frame, a significant size and bandwidth of memory is needed. If the current frame is compressed on-the-fly with RImCom or a similar solution and stored on DRAM, and the previous frame is read from DRAM and decompressed with a small IP block, then the overall system cost, power consumption, and electromagnetic radiation are reduced.     

Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model

A high performance digital architecture for the implementation of a nonlinear image enhancement technique is proposed in this paper. The image enhancement is based on an illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions. The algorithm shows robust performance with appropriate dynamic range compression, good contrast, accurate and consistent color rendition. The algorithm contains a large number of complex computations and thus it requires specialized hardware implementation for real-time applications. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Approximation techniques are used in the hardware algorithmic design to achieve high throughput. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 63 Mega-pixels (Mpixels) per second.     

A real-time inverse quantised transform for multi-standard with dynamic resolution support

In this paper, a real-time configurable intelligent property (IP) core is presented for image/video decoding process in compatibility with the standard MPEG-4 Visual and the standard H.264/AVC. The inverse quantised discrete cosine and integer transform can be used to perform inverse quantised discrete cosine transform and inverse quantised inverse integer transforms which only required shift and add operations. Meanwhile, COordinate Rotation DIgital Computer iterations and compensation steps are adjustable in order to compensate for the video compression quality regarding various data throughput. The implementations are embedded in publicly available software XVID Codes 1.2.2 for the standard MPEG-4 Visual and the H.264/AVC reference software JM 16.1, where the experimental results show that the balance between the computational complexity and video compression quality is retained. At the end, FPGA synthesised results show that the proposed IP core can bring advantages to low hardware costs and also provide real-time performance for Full HD and 4K–2K video decoding.     

The past, present, and future of image and multidimensional signalprocessing

The field of image and multidimensional signal processing began as a field of strong theoretical framework based on mathematics, statistics, and physics. Later, with advances in computing, memory, and image-sensing technology, techniques developed for image enhancement, still and moving image compression, image understanding gave this field a solid base of practical applications. Furthermore, the exploding growth of the Internet and the ubiquity of images and video, the field of image and multidimensional signal processing is becoming more and more exciting. Topics covered in the article include: multidimensional signal-processing theory, image acquisition, image transforms, image modeling, image enhancement and restoration, image and video analysis, processing, coding, hardware and software implementation issues, and computed imaging     

高效的H．264指数哥伦布解码器设计

H．264视频压缩标准凭借高压缩比和较好的图像质量，已经作为一种新型的标准被广泛接受。由于H.264的解码复杂度很高，软件实现难以满足实时性的要求，所以需要采用硬件解码。本文提出了一种针对H．264视频编码标准的可变长指数哥伦布码解码的硬件设计结构，给出了一种系统解码时间消耗与系统资源占用较少的硬件设计方案，最后给出了设计最终的仿真以及后端设计的结果。     

Synthesis of hardware models in C with pointers and complex datastructures

One of the greatest challenges in a C/C++-based design methodology is efficiently mapping C/C++ models into hardware. Many networking and multimedia applications implemented in hardware or mixed hardware/software systems now use complex data structures stored in multiple memories, so many C/C++ features that were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers for managing data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution, which fits current memory management methodologies, instantiates an application-specific hardware memory allocator coupled with a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. We present an implementation based on the SUIF framework along with case studies such as the realization of a video filter and an ATM segmentation engine     

雷达一次视频RTX实时传输和显示的软件实现

传统的一次视频实时传输、数字扫描变换及显示都是用硬件实现的,为节省成本、简化硬件配置,提出了一种通过RTX以太网实时传输、采用软件进行数字扫描变换和显示的实现方案。首先介绍了RTX实时操作子系统的特点,讨论了用RTTCP／IP协议传输一次视频并显示的可行性,并且给出了信号处理发送一次视频、显示系统RTX实时接收并显示的软件实现方法;最后通过实验验证了此方法的有效性。     

用ADSP21062高速信号处理系统实现机载SAR实时成像处理器的方位向处理

机载SAR实时成像处理器可以在载机飞行的同时获得高分辨率的SAR图像,对于实时监测、军事侦察等应用具有重要意义。实时成像处理器就是用高速数字信号处理系统来实时地实现SAR的成像算法。该文介绍SAR实时成像处理器方位向处理部分的研制,该部分采用了自行开发的、基于ADSP21062的高速信号处理系统,8片ADSP21062被安排在4个并行处理通道中,具有960MFLOPS的峰值处理速度,优化的软件设计保证了硬件资源的利用效率。仿真测试和外场实验证明了该系统的设计是成功的。该文对方位向处理部分的实现原理、硬件结构、软件设计进行了详细介绍。     

嵌入式远程视频监控系统的设计与实现

以S3C2410嵌入式处理器为核心,通过嵌入式多任务操作系统Linux采集摄像头视频数据,视频数据经JPEG算法压缩后通过网络实现远程传输。系统硬件主要包括CPUS3C2410、2片16Mx16型号为K4S561632C的SDRAM内存和16MByte型号为E28F128J3A150的NOR Flash固态存储器。系统软件设计主要包括构建ARM-Linux嵌入式软件平台．视频图像采集、压缩和网络传输的实现。实验表明,该设计达到预期目标,满足系统实时性要求,与传统PC机的监控系统相比,体积和成本分别减少75％和60％以上。     

Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors

Upcoming multi-media compression applications will require high memory bandwidth. In this paper, we estimate that a software reference implementation of an MPEG-4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352×288) Video Object Plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance.However, we also show that we can heavily improve on the memory transfers, without sacrificing speed (even gaining about 10% on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have manually applied an extended version of our data transfer and storage exploration (DTSE) methodology, which was originally developed for custom hardware implementations.     

嵌入式平台下的安全媒体传输系统

Security video communication is a challenging task, especially for wireless video applications. An efficient security multimedia system on embedded platform is designed. By analyzing the hardware architecture and resource, the efficient DSP-based H.264/AVC coding is studied by efficient video coding techniques and system optimizing implementation.To protect the confidentiality and integrity of media information, a novel security mechanism is presented, which includes user identify authentication and a perceptual video encryption algorithm based on exploiting the special feature of entropy coding in H.264. Experimental results show that the proposed hardware framework has high performance and achieves a better balance between security and efficiency. The proposed security mechanism can achieve high security and low complexity cost, and has a little effect on the compression ratio and transmission bandwidth. What’s more, encoding and encryption at the same time, the performance of data process can meet real-time application.     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

MPEG-4视频编解码器的DSP移植及优化

简要介绍了基于TMS320DM642的MPEG-4视频编解码器的硬件系统结构和软件任务流程,并重点阐述了MPEG-4视频编解码模块在DM642平台上的移植和优化.实验结果表明,移植和优化后可以实现视频的实时处理,并能保持较高的图像质量和压缩效率.     

基于提升小波变换的雷达视频数据实时压缩算法

雷达视频数据压缩具有大数据量、需要高保真度和实时处理的特点.而现有的一些高保真数据压缩算法都比较复杂,不能满足实时处理的要求.已有的硬件实现算法虽然可以实时处理,但其保真度差,同时难以调整压缩比.通过对实际雷达视频回波数据的分析,表明该数据具有相关性强、相关长度短的特点.在此基础之上,本文提出了一种基于提升格式5-3小波变换和简单的Golomb-Rice编码方法的压缩算法,该算法具有低复杂、高保真的特点,并对算法的运算量进行了详细地分析.实测实验表明,通过软件方式实现该算法即可满足雷达视频数据实时压缩的要求.最后,该算法已被成功应用到雷达海情记录系统中.     

基于ZYNQ的HDMI显示端设计与实现

高清晰度多媒体接口(High-Definition Multimedia Interface,HDMI)显示接口是嵌入式实现的视频采集及处理系统的重要组成部分,并有逐渐成为此类系统的显示端标准接口的趋势.然而在ZYNQ平台中由于没有在芯片中集成HDMI控制器,所以普遍采用模拟视频信号显示,限制了处理效果的展示和人机之间的交互.采用ADI的开源HDMI IP核以及Xilinx提供的相关IP核结合ADI HDMI发送器ADV7511,在ZYNQ平台上以软硬件协同的工作方式设计实现了HDMI显示端.方案分别基于无操作系统和Linux操作系统环境实现,其中无操作系统实现可以被移植用于一些特定场合或供硬件系统测试使用;而在Linux操作系统下,通过结合直接渲染管理器(Direct Rendering Manager,DRM),本方案可以方便Linux系统下该显示系统的移植与集成.     

图像采集卡在电视跟踪系统中的应用

为获得实时跟踪能力,提出一种新的基于MatroxOdyssey图像采集处理板卡的电视跟踪系统设计方案,完成系统的硬件及软件实现。系统通过图像采集卡采集视频,使用板卡开发库中提供的图像处理算法函数进行编程,完成对视频信号的实时采集与处理。系统实际使用中表现出了良好的性能。     

An Embedded Real-Time Surveillance System: Implementation and Evaluation

This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological operations, labeling and feature extraction are required to achieve the real-time performance while tracking will be handled in software in an embedded processor. By implementing a complete embedded system, bottlenecks in computational complexity and memory requirements can be identified and addressed. Accordingly, a memory reduction scheme for the video segmentation unit, reducing bandwidth with more than 70%, and a low complexity morphology architecture that only requires memory proportional to the input image width, have been developed. On a system level, it is shown that a labeling unit based on a contour tracing technique does not require unique labels, resulting in more than 50% memory reduction. The hardware accelerators provide the tracking software with image objects properties, i.e. features, thereby decoupling the tracking algorithm from the image stream. A prototype of the embedded system is running in real-time, 25 fps, on a field programmable gate array development board. Furthermore, the system scalability for higher image resolution is evaluated.     

基于OpenRISC1200的H.264视频解码器片上系统设计

新一代的压缩标准H.264以其高压缩率与高图像质量而备受青睐,将H.264集成于SoC(片上系统Sys-tern on chip)已成为必然的发展趋势.基于开源免费的32位OpenRISC1200 CPU,设计了H.264解码器SoC系统,系统以OpenRISC1200为核心控制模块,其他所有外围模块包括H.264解码...     

基于FPGA的微光视频采集与预处理系统设计

针对当前微光视频图像采集与处理系统中数据处理量与系统实时性之间的矛盾,设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的实时信号采集与预处理系统。该系统以高性能Xilinx A7系列芯片为主控芯片,使用两片第二代双倍数据率同步动态随机存取存储器(Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM)作为核心存储器件,并定制超感光互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)传感镜头作为视频图像采集器件。完成系统的硬件设计之后,通过Xilinx Vivado平台以及Matlab进行软件系统的工程设计与仿真分析,实现了微光环境下视频图像的采集、存储、处理与显示的全过程。实验结果表明,该系统采集的微光视频图像实时性好、动态画面流畅。