Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.     

A hot-carrier analysis of submicrometer MOSFET's

Based on Monte Carlo (MC) device simulations, an analysis of hot-carrier effects in submicrometer n-MOSFETs is presented that provides detailed insight because the high-energy electrons are treated directly. The DC stress characteristics of both lightly-doped drain (LDD) and conventional As source/drain devices are found to correlate with the surface hot-electron concentration, and agreement with experimental data shows that the electron flux above 3 eV, integrated along the channel, can be used to predict device degradation. The simulations indicate that the whole DC stress characteristic can be attributed to hot electrons, while the holes generated by impact ionization have a very small probability of gaining enough energy to be injected over the oxide barrier     

Analytical device model for submicrometer MOSFET's

A drain current model applicable to deep submicrometer MOSFETs is proposed. This pseudo-two-dimensional device model includes the velocity overshoot effect by using the extended-drift-diffusion (EDD) model. Calculated current-voltage characteristics agree well with the reported experimental data for deep submicrometer MOSFETs. The model is applicable to small-geometry MOSFETs down to L=0.1 μm, whereas conventional modes without the velocity overshoot are valid to 0.25 μm     

Modeling of submicrometer gate GaAs field effect transistors

Before describing the mainFet modelings today available, the main technological evolutions ofMesfet andTegfet are summarized. It is brought some information on the various physical effects that occur in the devices and that must be taken into account in the models. It is shown that the different kinds of modelings (Monte Carlo, two dimensional, one dimensional) constitute a continuous chain, where the different elements appear strictly complementary. Finally, the present situation concerning modeling ofMesfet andTegfet will be presented.     

Microwave operation of submicrometer channel-length Silicon MOSFET's

Aluminum-gate silicon n-channel MOSFET's with channel lengths down to 0.5 µm have been fabricated. A simple four-mask process based on contact optical lithography was used. Partial self-alignment of the gate to the channel could be achieved because of an enhanced oxidation rate over the source/drain due to the heavy arsenic implantation. Accordingly, parasitics were minimized and the devices showed excellent microwave performance withf_{max}and fTnear 20 GHz.     

Analysis and control of floating-body bipolar effects in fullydepleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible     

An optimally designed process for submicrometer MOSFET's

An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 µm. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.     

Thermal-oxide gate GaAs MOSFET's

The first thermal-oxide gate GaAs MOSFET of the deep-depletion mode is reported. The gate oxide, which has been grown by the new GaAs oxidation technique in the As2O3vapor, is so chemically stable that it can be subjected to the fabrication process. Measurement of some dc characteristics of the device fabricated has shown a strikingly suppressed hysteresis.     

Two-dimensional numerical analysis of the narrow gate effect in MOSFET

Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.     

Ultrathin oxide-nitride gate dielectric MOSFET's

The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents     

Scaling issues related to high field phenomena in submicrometer MOSFET's

Both enhancement and depletion n-channel MOS devices with electrical channel lengths between 1 and 0.3 µm are characterized in terms of carrier heating effects. The effect of gate oxide thickness on the two-dimensional (2-D) electric field distribution has been analyzed through 2-D numerical device simulation, and its impact on carrier heating process has been experimentally quantified. Our results allow some conclusions for reduced supply voltages (2 and 3 V for temperatures of 77 and 300 K, respectively) for future NMOS technologies with design rules of 0.75 µm.     

An analytical drain current model for submicrometer and deepsubmicrometer MOSFET's

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

An energy-dependent two-dimensional substrate current model for thesimulation of submicrometer MOSFET's

A multicurrent contour, average-energy-based, substrate current model for silicon submicrometer NMOSFETs is presented as a significant improvement to the local-field model that is commonly used in modern drift-diffusion device simulators. The model is implemented as a post-processor by applying a one-dimensional energy conservation equation to many current contours in order to generate a two-dimensional representation of average energy and impact ionization rate which is integrated to calculate the substrate current. Comparisons of simulations and experimental I-V curves for both simple and LDD MOSFETs are presented. Outstanding agreement has been obtained over a wide range of bias conditions and channel lengths     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Submicron gate MOSFET's with channel-doped separate gate structures (SG-MOSFET's)

Submicron gate MOSFET's with a new device structure are presented. The device features gate separation between the source and gate and between the gate and drain. The minimum gate length limited by VTHlowering is extended into the submicron range. Experimental results showed pentode-like current-voltage characteristics without punchthtough, even in the submicron range. Experimental results of inverter circuits and theoretical analysis predict high-speed operation in the subnanosecond region.     

Width dependence of substrate and gate currents in MOSFET's

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified