Reliable multistage interconnection network design

High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.     

Disjoint path properties of the data manipulator network family

A critical component of any parallel processing system is the interconnection network that provides communications among the system's processors and memories. The data manipulator (gamma) network family is an important class of multistage interconnection networks that is being studied by various researchers. One interesting property of the data manipulator network family is the existence of multiple paths through the network for most source/ destination pairs. The condition that must be present to have disjoint paths through the network for a given source/ destination pair is shown, where disjoint paths are multiple paths with no links in common. It is derived that the maximum number of disjoint paths for any source/destination pair is two and a method for finding the routing tags that specify these paths is given. For source/destination pairs that have disjoint paths, a single fault cannot prevent communication between that source/ destination pair. The effect of a fault in a given stage of the network on the number of source/destination pairs that can be connected is also discussed. All results are proven mathematically.     

CGIN: a fault tolerant modified Gamma interconnection network

To improve the terminal reliability of the Gamma interconnection network (GIN), we consider altering its connecting patterns between stages to attain multiple disjoint paths between any source and destination pair. The new modified GIN, referred to as a CGIN with connecting patterns between stages exhibiting a cyclic feature, is able to tolerate any arbitrary single fault and to lift up terminal reliability accordingly. If several rows of switching elements are fabricated in one chip using the VLSI technology, a CGIN could lead to reduced cost because the pin count per chip decreases and the layout area taken by connections shrinks. To make routing and rerouting in the CGIN more efficient and simpler to implement, destination tag routing and rerouting is also provided     

Improved extra group network: a new fault-tolerant multistage interconnection network

Supersystems are shown to provide enough computational power to solve complex problems on a real-time basis. In all these systems, the computational parallelism is obtained from multiple processors. Multistage interconnection networks (MINs) play a vital role on the performance of these multiprocessor systems. This paper introduces a new fault-tolerant MIN named as improved extra group network (IEGN). IEGN is designed by existing extra group (EGN) network, which is a regular multipath network with limited fault tolerance. IEGN provides four times more paths between any source–destination pairs compared with EGN. The performance of IEGN has been evaluated in terms of permutation capability, fault tolerance, reliability, path length, and cost. It has also been proved that the IEGN can achieve better results in terms of fault tolerance, reliability, path length and cost-effectiveness, in comparison to known networks, namely, EGN, augmented baseline network, augmented shuffle-exchange network, fault-tolerant double tree, Benes network, and Replicated MIN.     

A Kind of Multistage Interconnection Networks with Multiple Paths

1ThisworkwassupportedbytheNationalNaturalScienceFoundationofChina,GralltNo.69473024.1IntroductionMultiprocessorsystemsoftenuseinterconnectionnetworkstoconnectproces-sorsormemorymodules-Atime-sharedbusisthesimplestformofinterconnectionnetworks,butitcannotprovidetheperformancerequiredinmultiprocessorsystemstoday.Acrossbarswitchnetworkisanalternativeusedintheearliersystemstoimplementinterconnection.Theonlydelaytoconnectinputstooutputsisthatofasingleswitchinggate,butacrossbarswitchnetworkisver…     

A Kind of Multistage Interconnection Networks with Multiple Paths

Mltistage Interconnection Networks(MINs)are orten used to provide interconnections in multiprocessor systems.A unique path MIN usually has lower hardware complexity and a simple control algorithm,but it lacks fault tolerance.This paper proposes a kind of multipat MINs,which are obtained by adding auxiliary links at the final stage in Quad Tree(QT) networks so that they can provide more paths between each source-destination pair,and presents their routing algorithm which is both destination tag based and adaptive.Starting with the routing tag for the minimum path between a given source-destination pair,the routing algorithm uses a set of rules to select switches and modify routing tag.In addition to trying the auxiliary link when link0 an link1 are unavilable,link1 will be tried when link0 ys unavailable.This feature distinguishing the proposed routing algorithm form that for QT networks makes better use of all the possible paths between the given source-destination pair.In the end,this paper introduces a performance index,which is called capacity,to compare different kinds of MINs .Comparison shows that the proposed MINs have better capacity than QT networks.     

Designing a Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network with Disjoint Paths

Multi-stage Interconnection Networks (MINs) are designed to achieve fault-tolerance and collision solving by providing a set of disjoint paths. Ching-Wen Chen and Chung-Ping Chung had proposed a fault-tolerant network called Combining Switches Multi-stage Interconnection Network (CSMIN) and an inaccurate algorithm that provided two correct disjoint paths only for some source-destination pairs. This paper provides a more comprehensive and accurate algorithm that always generate correct routing-tags for two disjoint paths for every source-destination pair in the CSMIN. The 1-fault tolerant CSMIN causes the two disjoint paths to have regular distances at each stage. Moreover, our algorithm backtracks a packet to the previous stage and takes the other disjoint path in the event of a fault or a collision in the network. Furthermore, to eliminate the backtracking penalties of CSMIN, we propose a new design called Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network (FCSMIN). It has similar characteristics of 1-fault tolerance and two disjoint paths between any source-destination pair, but it can tolerate only one link or switch fault at each stage without backtracking. Our simulation and comparative analysis result shows that FCSMIN has added advantages of destination-tag routing, lower hardware costs, strong reroutability, lower preprocessing overhead, and higher fault-tolerance power in comparison to CSMIN.     

Performance of multistage bus networks for a distributed sharedmemory multiprocessor

A multistage bus network (MEN) is proposed to overcome some of the shortcomings of the conventional multistage interconnection networks (MINs), single bus, and hierarchical bus interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the MINs and has the same bandwidth at each stage. A switch in an MBN is similar to that in a MIN switch except that there is a single bus connection instead of a crossbar. MBNs support bidirectional routing and there exists a number of paths between any source and destination pair. The authors develop self routing techniques for the various paths, present an algorithm to route a request along the path with minimum distance, and analyze the probabilities of a packet taking different routes. Further, they derive a performance analysis of a synchronous packet-switched MBN in a distributed shared memory environment and compare the results with those of an equivalent bidirectional MIN (BMIN). Finally, they present the execution time of various applications on the MBN and the BMIN through an execution-driven simulation. They show that the MBN provides similar performance to a BMIN while offering simplicity in hardware and more fault-tolerance than a conventional MIN     

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

In fault-tolerant multistage interconnection design, the method of providing disjoint paths can tolerate faults, but it is complicated and hard to choose a collision-free path in disjoint paths networks. A network with disjoint paths can concurrently send more identical packets from the source node to increase the arrival ratio or backtrack a packet to the source and take the other disjoint path, but these two methods might increase the collision ratio. In contrast, a dynamic rerouting method finds an alternative path that tolerates faults or prevents collisions. In this paper, we present methods of designing dynamic rerouting networks. This paper presents (1) three design schemes of dynamic rerouting networks to tolerate faults and prevent collisions; (2) design schemes that enable a dynamic rerouting network to use destination tag routing to save hardware cost in switches for computing rerouting tags; (3) a method to prevent a packet from re-encountering the faulty element again after rerouting to reduce the number of rerouting hops and improve the arrival ratio; and (4) simulation results of related dynamic rerouting networks to realize the factors which influence the arrival ratio including the fault tolerant capability and the number of rerouting hops. According to our proposed design schemes and according to our analysis and simulation results, a designer can choose an applicable dynamic rerouting network by using cost-efficient considerations. This paper was partially supported by the National Science Council NSC-92-2213-E-324-006- and NSC-94-2213-E-035-050-; and the partial part of the preliminary version of this paper was published by the conference ISPA 2005 [5].     

The composite banyan network

A new multipath multistage interconnection network called the composite banyan network is proposed. The network incorporates both the banyan and the reverse banyan networks and is constructed by superimposing the two. The basic building blocks in the composite banyan network are 3×3 switching elements with log₂N stages. A major advantage of the composite banyan network over existing networks with 3×3 SEs is an efficient and fast control algorithm that sets up a path between any source and destination pair. Instead of complex numerical calculations, the network can easily generate a primary routing tag and alternate tags through simple binary operations. Also, the network has a lot of favorable features, including regularity, symmetry, and easy rerouting capability under faults and conflicts. It is shown that at least two totally disjoint paths exist between any source and destination pair, which increase the degree of fault-tolerance. A deterministic permutation routing algorithm is also developed for the 8×8 composite banyan network, Using a simple tabular method, it is shown that the algorithm always finds a set of conflict-free tags     

A new family of interconnection networks of fixed degree three

A new family of interconnection networks WGn is proposed, that is constant degree 3 Cayley graph, and is isomorphic to a Cayley graph of the wreath product Z2 Sn when the generator set is chosen properly. Its different algebraic properties is investigated and a routing algorithm is given with the diameter upper bounded by 3n2 - 6n 4. The embedding properties and the fault tolerance are devired. In conclusion, we present a comparison of some familiar networks with constant degree 3.     

Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving

In fault-tolerant interconnection designs, many prior researches suggest good use of disjoint paths to improve the reliability of interconnection networks. Although disjoint paths increase reliability, they always cost the throughput penalty. To address the problems of both performance and fault-tolerant capability, the following issues should be carefully considered: (1) guarantee of at least two disjoint paths, (2) easy rerouting between disjoint paths, (3) keep low rerouting hops, (4) solve the occurrences of packets’ collision. In this paper, we consider these issues to design a fault-tolerant network called CSMIN (Combining Switches Multistage Interconnection Network). CSMIN provides two disjoint paths to guarantee one fault-tolerant and can dynamically reroute packets between these two paths to solve the collision situation. In other words, to switch packets between these two disjoint paths easily, CSMIN causes these two disjoint paths to have regular distances at each stage. Accordingly, a packet can be dynamically sent to the other disjoint path if it encounters a faulty or busy element. In addition, CSMIN presents low rerouting hops (an average of one rerouting hop) to maintain a low collision ratio. From the simulation result, CSMIN performs with a better arrival ratio than Gamma and other related disjoint paths networks do.This research was supported by the National Science Council NSC-91-2218-E-324-006.     

MPE2S: 基于多路径纠删编码的无线传感器网络可靠传输策略

传输可靠性是衡量无线传感器(Wireless sensor networks, WSN)网络性能的一个重要指标. 针对节点故障会影响网络传输稳定性和可靠性的问题, 提出了基于多路径纠删编码的 无线传感器网络可靠传输策略(Multi-paths and erasure encoding strategy, MPE2S). 根据反映链路质量的最优最差蚂蚁系统的信息素归一化值, 在相邻等级节点间建立多条互不交叉的传输路径, 将源数据包经纠删编码的 数据片沿多条路径分配和传输以实现负载均衡和故障容错. 理论分析和仿真结果表明,MPE2S具有较高数据包接收率、数据准确率和能效性, 体现了良好的故障容错性、数据传输稳定性和可靠性.     

A new family of Cayley graph interconnection networks of constantdegree four

We propose a new family of interconnection networks that are Cayley graphs with constant node degree 4. These graphs are regular, have logarithmic diameter, and are maximally fault tolerant. We investigate different algebraic properties of these networks (including fault tolerance) and propose optimal routing algorithms. As far as we know, this is the first family of Cayley graphs of constant degree 4     

Many-to-many disjoint path covers in hypercube-like interconnection networks with faulty elements

A many-to-many k-disjoint path cover (k-DPC) of a graph G is a set of k disjoint paths joining k distinct source-sink pairs in which each vertex of G is covered by a path. We deal with the graph G/sub 0/ /spl oplus/ G/sub 1/ obtained from connecting two graphs G/sub 0/ and G/sub 1/ with n vertices each by n pairwise nonadjacent edges joining vertices in G/sub 0/ and vertices in G/sub 1/. Many interconnection networks such as hypercube-like interconnection networks can be represented in the form of G/sub 0/ /spl oplus/ G/sub 1/ connecting two lower dimensional networks G/sub 0/ and G/sub 1/. In the presence of faulty vertices and/or edges, we investigate many-to-many disjoint path coverability of G/sub 0/ /spl oplus/ G/sub 1/ and (G/sub 0/ /spl oplus/ G/sub 1/) /spl oplus/ (G/sub 2/ /spl oplus/ G/sub 3/ ), provided some conditions on the Hamiltonicity and disjoint path coverability of each graph G/sub i/ are satisfied, 0 /spl les/ i /spl les/ 3. We apply our main results to recursive circulant G(2/sup m/, 4) and a subclass of hypercube-like interconnection networks, called restricted HL-graphs. The subclasses includes twisted cubes, crossed cubes, multiply twisted cubes, Mobius cubes, Mcubes, and generalized twisted cubes. We show that all these networks of degree m with f or less faulty elements have a many-to-many k-DPC joining any k distinct source-sink pairs for any k /spl ges/ 1 and f /spl ges/ 0 such that f+2k /spl les/ m - 1.     

Fault-tolerant routing over shortest node-disjoint paths in hypercubes

This paper presented a routing algorithm that finds n disjoint shortest paths from the source node s to target node d in the n-dimensional hypercube. Fault-tolerant routing over all shortest node-disjoint paths has been investigated to overcome the failure encountered during routing in hypercube networks. In this paper, we proposed an efficient approach to provide fault-tolerant routing which has been investigated on hypercube networks. The proposed approach is based on all shortest node-disjoint paths concept in order to find a fault-free shortest path among several paths provided. The proposed algorithm is a simple uniform distributed algorithm that can tolerate a large number of process failures, while delivering all n messages over optimal-length disjoint paths. However, no distributed algorithm uses acknowledgement messages (acks) for fault tolerance. So, for dealing the faults, acknowledgement messages (acks) are included in the proposed algorithm for routing messages over node-disjoint paths in a hypercube network.     

Fault-tolerant real-time communication in distributed computingsystems

The delivery delay in a point-to-point packet switching network is difficult to control due to the contention among randomly-arriving packets at each node and multihops a packet must travel between its source and destination. Despite this difficulty, there are an increasing number of applications that require packets to be delivered reliably within prespecified delay bounds. This paper shows how this can be achieved by using real-time channels which make “soft” reservation of network resources to ensure the timely delivery of real-time packets. We first present theoretical results and detailed procedures for the establishment of real-time channels and then show how the basic real-time channels can be enhanced to be fault-tolerant using the multiple disjoint paths between a pair of communicating nodes. The contribution of the former is a tighter schedulability condition which makes more efficient use of network resources than any other existing approaches, and that of the latter is a significant improvement in fault tolerance over the basic real-time channel, which is inherently susceptible to component failures     

General-demand disjoint path covers in a graph with faulty elements

A k-disjoint path cover of a graph is a set of k internally vertex-disjoint paths which cover the vertex set with k paths and each of which runs between a source and a sink. Given that each source and sink v is associated with an integer-valued demand d(v)≥1, we are concerned with general-demand k-disjoint path cover in which every source and sink v is contained in the d(v) paths. In this paper, we present a reduction of a general-demand disjoint path cover problem to an unpaired many-to-many disjoint path cover problem, and obtain some results on disjoint path covers of restricted HL-graphs and proper interval graphs with faulty vertices and/or edges.     

二进制递归网络的连通性

二进制递归网络是超立方体的一类特殊变体,它具有很多良好的网络特性。网络的连通性是衡量网络结构通信能力的一个重要性能,虽然到目前为止已知的一些二进制递归网 络的连通性都已被研究过,但这些研究只是针对个体进行的,并不能代表所有二进制递归网络的连通特性。本文通过证明任何一个二进制递归网络中的每对顶点之间只能存在在”条顶点不交路,得到了整个二进制递归网络的点和边连通度皆为”的重要结论。     

A regular scalable fault tolerant interconnection network for distributed processing

Bounded degree networks like deBruijn graphs or wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing nodes in the interconnection networks can have only a fixed number of I/O ports. One basic drawback of these networks is that they cannot provide a desired level of fault tolerance because of the bounded degree of the nodes. On the other hand, networks like hypercube (where degree of a node grows with the size of a network) can provide the desired fault tolerance but the design of a node becomes problematic for large networks. In their attempt to combine the best of the both worlds, authors in [IEEE Transactions on Parallel and Distributed Systems 4(9) (1993) 962] proposed hyper-deBruijn (HD) networks that have many additional features of logarithmic diameter, partitionability, embedding, etc. But, HD networks are not regular, are not optimally fault tolerant and the optimal routing is relatively complex. Our purpose in the present paper is to extend the concepts used in the above-mentioned reference to propose a new family of scalable network graphs that retain all the good features of HD networks and at the same time are regular and maximally fault tolerant; the optimal point to point routing algorithm is significantly simpler than that of the HD networks. We have developed some new interesting results on wrapped butterfly networks in the process.