ZnO as a dielectric for organic thin film transistor-based non-volatile memory

This paper demonstrates the novel application of d.c. sputtered zinc oxide (ZnO) as a charge trapping dielectric material for the application of an organic thin film transistor (OTFT) based non-volatile memory (NVM). The motivation of using ZnO as a dielectric is due to its chemical stability and optical transparency, enabling future development of transparent electronic devices. Unbalanced magnetron d.c. sputtering with Ar:O₂ ratio of 80:20 was used to obtained a ZnO dielectric of 50 nm thick. The ZnO has an optical band gap of 3.23 eV, resistivity and k-value of 5 × 10⁷ Ω-cm and 50, respectively. The ZnO sandwiched between two layers of low-k methyl-silsesquioxane (MSQ) sol–gel dielectric creates a triple layer dielectric structure for charge storage. A solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene, was used as an active layer of an OTFT-NVM. It has been successfully demonstrated that this OTFT-NVM can be electrically programmed and erased at a low voltage.     

电荷俘获存储器阻挡层研究进展

随着非挥发性存储器(NVM)存储单元的特征尺寸进入20 nm节点,使用单层SiO2作为阻挡层的传统电荷俘获存储器结构性能上逐渐受到限制。基于阻挡层在存储器栅堆栈中的作用与基本要求,首先,指出单层SiO2作为阻挡层存在的主要问题,然后对高介电常数材料作为阻挡层时,其禁带宽度、介电常数、内部的缺陷密度以及退火工艺等方面对存储特性的影响进行了分析,同时对近年来研究较多的阻挡层能带工程进行了详细介绍,如SiO2和Al2O3的复合阻挡层结构、多层高介电常数材料的阻挡层结构等。最后,对目前研究进展中存在的问题以及未来的研究方向和趋势进行了总结和展望。     

Controlled growth of a graphene charge-floating gate for organic non-volatile memory transistors

We report memory application for graphene as a floating gate in organic thin-film transistor (OTFT) structure. For graphene floating gate, we demonstrate a simpler synthesis method to form a discrete graphene layer by controlling the growth time during a conventional CVD process. The resulting organic memory transistor with the discrete graphene charge-storage layer is evaluated. The device was demonstrated based on solution-processed tunneling dielectric layers and evaporated pentacene organic semiconductor. The resulting devices exhibited programmable memory characteristics, including threshold voltage shifts (∼28 V) in the programmed/erased states when an appropriate gate voltage was applied. They also showed an estimated long data retention ability and program/erase cycles endurance more than 100 times with reliable non-volatile memory properties although operated without encapsulation and in an ambient condition.     

Energy transfer in organic multilayer quantum well structure and its application to OLEDs

We fabricate a series of samples and OLEDs with organic multilayer quantum well structure, which consist of alternate PBD and Alq3. Both PBD and Alq3 are electron-transporting materials, and PBD is used as potential barrier layer, while Alq3 is used as potential well layer and emitting layer. Compared with double-layer structure, the luminescent characteris- tics of organic samples and diodes with quantum well structure are investigated and the quantum well structure helps the energy transfer between well layer and barrier layer. The quantum well structure makes carriers disperse in the different well layers and then increases the number of excitons to enhance the efficiency of the recombination.     

Highly Reliable Charge Trap-Type Organic Non-Volatile Memory Device Using Advanced Band-Engineered Organic-Inorganic Hybrid Dielectric Stacks

With the recent interest in data storage in flexible electronics, highly reliable charge trap-type organic-based non-volatile memory (CT-ONVM) has attracted much attention. CT-ONVM should have a wide memory window, good endurance, and long-term retention characteristics, as well as mechanical flexibility. This paper proposed CT-ONVM devices consisting of band-engineered organic–inorganic hybrid films synthesized via an initiated chemical vapor deposition process. The synthesized poly(1,3,5-trimethyl-1,3,5,-trivinyl cyclotrisiloxane) and Al hybrid films are used as a tunneling dielectric layer and a blocking dielectric layer, respectively. For the charge trapping layer, different Hf, Zr, and Ti hybrids are examined, and their memory performances are systematically compared. The best combination of hybrid dielectric stacks showed a wide memory window of 6.77 V, good endurance of up to 10⁴ cycles, and charge retention of up to 71% after 10⁸ s even under the 2% strained condition. The CT-ONVM device using the hybrid dielectric stacks outperforms other organic-based charge trap memory devices and is even comparable in performance to conventional inorganic-based poly-silicon/oxide/nitride/oxide/silicon structures devices. The CT-ONVM using hybrid dielectrics can overcome the inherent low reliability and process complexity limitations of organic electronics and expedite the realization of wearable organic electronics.     

Effects of film microstructure on the bias stability of pentacene field-effect transistors

In this report, the effects of film microstructure on the bias stability of pentacene field-effect transistors (FETs) were investigated. To control the microstructure of pentacene film, substrate temperature was changed from 25 to 90 °C during pentacene deposition. As the substrate temperature increased, pentacene grain size increased (or grain boundary (GB) decreased) because of the elevated surface diffusion of pentacene molecules. Accordingly, field-effect mobility increased up to 1.52 cm²/V. In contrast, bias stability showed totally different characteristics: samples prepared at high substrate temperatures exhibited the lowest degree of bias stability. This GB independent charge trapping phenomenon was solved by examining molecular scale ordering within the intragrain regions. The pentacene film grown at 90 °C showed the largest percentage of pentacene molecules with bulk crystalline structures. This inhomogeneity in the pentacene microstructure induces crystal mismatch within intragrain region, thereby providing deep trap sites for gate-bias stress driven instability. Our study shows that GB is not the main sites for bias stress related charge trapping, rather the molecular orientation within intragrain region is responsible for the charge trapping events. In this regard, the control of molecular scale ordering is important to obtain OFETs with a high bias stability.     

Organic field-effect transistors and memory elements using deoxyribonucleic acid (DNA) gate dielectric

Deoxyribonucleic acid (DNA) bio-polymers derived from fish waste products are employed as gate dielectric in n-type methanofullerene as well as p-type pentacene based organic field-effect transistors working at low voltage levels and low gate leakage currents. Based on the large hysteresis in the transfer characteristics, operation of the transistor as a non-volatile memory element is shown. Practically hysteresis free operation of DNA based transistors is obtained at low voltage levels by adding an additional aluminium oxide blocking layer between the organic semiconductor and the DNA gate dielectric.     

Nonvolatile Charge Injection Memory Based on Black Phosphorous 2D Nanosheets for Charge Trapping and Active Channel Layers

2D van der Waals atomic crystal materials have great potential for use in future nanoscale electronic and optoelectronic applications owing to their unique properties such as a tunable energy band gap according to their thickness or number of layers. Recently, black phosphorous (BP) has attracted significant interest because it is a single‐component material like graphene and has high mobility, a direct band gap, and exhibits ambipolar transition behavior. This study reports on a charge injection memory field‐effect transistor on a glass substrate, where few‐layer BPs act as the active channel and charge trapping layers, and Al₂O₃ films grown by atomic layer deposition act as the tunneling and blocking layers. Because of the ambipolar properties of BP nanosheets, both electrons and holes are involved in the charge trapping process, resulting in bilateral threshold voltage shifts with a large memory window of 22 V. Finally, a memory circuit of a resistive‐load inverter is implemented that converts analog signals (current) to digital signals (voltage). Such a memory inverter also shows a clear memory window and distinct memory on/off switching characteristics.     

High-response organic thin-film memory transistors based on dipole-functional polymer electret layers

A molecular design for the electret material of n-operating organic field-effect transistor-based (OFET) memories is introduced. A large memory window and high operating speed were achieved while the polar groups are connected to the polymer chain of polyimide, which plays the role of electret of a transistor memory device. The phase variation of electrical force microscopy images showed that polarization field induces charge trapping states on the surface of electret layer and accumulates charged carriers within the conducting channel of OFET to achieve high-performance memory and transistor simultaneously. An extra-large memory window was also obtained by introducing photo-induced charge transfer effect.     

Tris（8—Hydroxyquinoline）Aluminum／2—（4—Biphenylyl）—5—（4—Tertbutylphenyl）—1,3,3—O—xadiazole Organic Multiple Quantum Wells for Electroluminescent Devices

Organic multiple quantum wells(OMQWs) consisting of alternating layers of organic materials have been fabricated from tris(8-hdroxyquinoline) aluminum(Alq)and 2-(4-biphenylyl)-5-(4-tertbutylphenyl)-1,3,3-oxadiazole(PBD)by a multisource-type high-vacuum organic molecular deposition.From the small-angle X-ray diffraction patterns of Alq/PBD OMQWs,a periodically layered structure is confirmed through the entire stack.The Alq layer thickness in the OMQWs was varied from 1 nm to 4 nm.From the optical aborption, photoluminescence and electroluminescence measurements,it is found that the exciton energy shifts to higher energy with decreasing Alq layer thickness,The changes of the exciton energy could be interpreted as the confinement effects of exciton in the Alq thin layers.Narrowing of the emission spectrum has also been observed for the electroluminescent devices(ELDs)with the OMQWs structure at room temperature.     

High efficiency fluorescent white organic light-emitting diodes having a yellow fluorescent emitter sensitized by a blue thermally activated delayed fluorescent emitter

Fluorescent white organic light-emitting diodes having a blue thermally activated delayed fluorescent emitter and a yellow fluorescent emitter was developed by co-doping the blue and yellow emitters in a single emitting layer. The blue delayed fluorescent device showed high quantum efficiency of 22.6% at a very high doping concentration of 50% and the white devices exhibited a high quantum efficiency of 15.5% even though a fluorescent yellow emitter was doped in the blue thermally activated delayed fluorescent emitting layer. Minimized charge trapping and Dexter energy transfer by low yellow doping concentration of 0.05% as well as efficient Förster energy transfer could develop the high efficiency fluorescent white organic light-emitting diodes.     

Molecular-scale charge trap medium for organic non-volatile memory transistors

In this work, we introduce a molecular-scale charge trap medium for an organic non-volatile memory transistor (ONVMTs). We use two different types of small molecules, 2,3,6,7,10,11-hexahydroxytriphenylene (HHTP) and 2,3,6,7,10,11-hexamethoxytriphenylene (HMTP), which have the same triphenylene cores with either hydroxyl or methoxy end groups. The thickness of the small molecule charge trap layer was sophisticatedly controlled using the thermal evaporation method. X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared (FTIR) analysis revealed that there were negligible differences in the chemical structures of both small molecules before and after thermal deposition process. The ONVMTs with a 1-nm-thick HHTP charge trap layer showed a large hysteresis window, approximately 20 V, under a double sweep of the gate bias between 40 V and −40 V. The HMTP-based structure showed a negligible memory window, which implied that the hydroxyl groups affected hysteresis. The number of trapped charges on the HHTP charge trap layer was measured to be 4.21 × 10¹² cm⁻². By varying the thickness of the molecular-scale charge trap medium, it was determined that the most efficient charge trapping thickness of HHTP charge trap layer was approximately 5 nm.     

High-speed InP/InGaAs avalanche photodiodes with a compositionallygraded quaternary layer

InP/InGaAs avalanche photodiodes (APDs) with a compositionally graded quaternary layer at the heterointerface between the InGaAs absorption and InP multiplication regions were fabricated and tested. A comparison of samples with the graded layer and with conventional three quaternary layers showed that the frequency characteristics for samples with the graded layer did not deteriorate at a low bias voltage even below -100°C, unlike APDs with three InGaAsP layers. Thus, no hole trapping occurred at the InP/InGaAs heterointerface with the graded layer. A sample with the graded layer showed a cutoff frequency exceeding 9 GHz at a low multiplication factor of 2. The authors found InP/InGaAs APDs with the compositionally graded quaternary layer to be useful over a wide temperature range     

Enhanced brightness and efficiency of organic light-emitting diodes with an LiF in the Alq/sub 3/

Highly efficient and bright organic light-emitting diodes have been realized by inserting a thin insulating lithium fluoride (LiF) layer in the tris-(8-hydroxyquinoline) aluminum (Alq/sub 3/) with conventional organic layers. By comparing the performances of newly devised devices as a function of the position of the LiF in the Alq/sub 3/ layer, the authors propose the optimal position of the LiF in the Alq/sub 3/ layer. Experimental results show that the efficiency and brightness of the newly devised device with LiF in the Alq/sub 3/ layer were seven times higher than that without LiF in the Alq/sub 3/ layer.     

Electrical bistability,negative differential resistance and carrier transport in flexible organic memory device based on polymer bilayer structure

Bistable nonvolatile memory devices containing two different layers of polymers, viz. MEH-PPV (poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenyl vinylene]) and PEDOT:PSS (poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)) has been fabricated by a simple spin-coating technique on flexible polyimide (PI) substrates with a structure Al/MEH-PPV/PEDOT:PSS/Ag-Pd/PI. The current–voltage measurements of the as-fabricated devices showed a nonvolatile electrical bistability with electric field induced charge transfer through the polymer layers and negative differential resistance (NDR) which is attributed to the charge trapping in the MEH-PPV layer. The current ON/OFF ratio between the high-conducting state (ON state) and low-conducting state (OFF state) is found to be of the order of 10³ at room temperature which is comparable to organic field effect transistor based memory devices. We propose that such an improvement of rectification ratio (ON/OFF ratio) is caused due to the inclusion of PEDOT:PSS, which serves as a conducting current path for carrier transport; however, NDR is an effect of the trapped charges in the MEH-PPV electron confinement layer. The device shows excellent stability over 10⁴ s without any significant degradation under continuous readout testing in both the ON and OFF states. The carrier transport mechanism of the fabricated organic bistable device has been explained on the basis of different conduction mechanisms such as thermionic emission, space-charge-limited conduction, and Fowler–Nordheim tunneling. A band diagram is proposed to explain the charge transport phenomena. These bilayer structures are free from the drawbacks of the single organic layer based memory devices where the phase separation between the nanoparticles and polymers leads to the degradation of device stability and lifetime.     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices

Charge trapping flash memory devices are susceptible to charge loss mechanisms induced by high energy irradiation such as thermal neutrons, X-rays, and gamma ray. The loss of trapped charges due to charge loss mechanism has resulted in the degradation in data retention performance and unwanted read failures in field applications. In this work, charge loss mechanisms of nanoscale nitride based charge trapping flash memory devices due to irradiation of high energy X-rays were carefully studied and examined. Nitride based charge trapping flash memory device stored charges in the nitride storage layer of an Oxide-Nitride-Oxide stack. Threshold voltage of the nitride based charge trapping flash memory cells were collected before and after X-ray irradiation done onto the memory devices. Threshold voltage distributions have shown that significant number of cells at the lower end of the program distribution had perturbed from the overall distribution that was caused by X-ray irradiation induced charge loss mechanism. In this study, the effect of the use of 300 μm Zn filter and its proximity to the device under study to mitigate the X-ray irradiation induced charge loss was also thoroughly elucidated. The results have demonstrated that 300 μm Zn filter has significantly improved the immunity of nitride based charge trap flash memory device up to 6.446 times. However, the proximity of the Zn filter to the flash memory device exacerbated up to 7.4280 times due to the impact of secondary effect in X-ray fluorescence to the device under study. Hence, this investigation concluded that X-ray irradiation is a genuine reliability concern for nanoscale nitride based charge trapping flash memory devices. Furthermore, it is recommended to place Zn filter close to X-ray source to significantly mitigate the Vt distribution drift induced by X-ray irradiation.     

Effect of thickness of polymer electret on charge trapping properties of pentacene-based nonvolatile field-effect transistor memory

In this report, a set of pentacene-based organic field-effect transistor (OFET) memory devices using different thicknesses (ranged from 17.8 to 100.4 nm) of Poly (N-vinylcarbazole) (PVK) as charge trapping layers were fabricated, and the dependences of thickness on charge trapping behaviors were systematically investigated. As the thickness increased, the charge trapping capacity shows a Gaussian distributed growth behavior while the surface tunneling distance demonstrates the property of exponential decrease, which is ascribed to the synergistic effects of potential redistribution of trapped charge carriers and the co-existence of direct tunneling and Fowler–Nordheim (FN) tunneling. The optimum thickness (d_ot) to possess the most efficient charge trapping properties, which means a reasonably low programming voltage and high charge trapping capacity with good bias stress stability, is approximately 40 ± 5 nm. By calculating the threshold thickness (d_th) of PVK for an ultrathin memory, we proposed a model of superficial tunneling distance to deconstruct the continuous chargeable polymer electret-based OFET memory. Our work provided a quantitative evaluation method and can improve the understanding of charge trapping process from the aspect of electret thickness.     

Role of tunneling layer in graphene-oxide based organic nonvolatile memory transistors

This paper demonstrates non-volatile memory transistor using solution processable graphene oxide (GO) as charge storage nodes in the configuration, p⁺⁺Si/SiO₂/GO/Tunneling layer/Pentacene/Au. The tunneling layers are polymethylmethacrylate (PMMA) and polyvinylphenol (PVP). GO film could be deposited as single layered flakes with a uniform distribution using spin coating technique. The devices with PMMA as charge tunneling layer exhibited higher mobility and on/off ratio than PVP based devices. The devices show a large positive threshold voltage shift (∼24 V for PMMA and ∼15 V for PVP) from initial value during programming at gate voltage of +80 V kept for 10 s. The transfer curves can be restored approximately to its initial condition by applying an erasing voltage of −30 V for 10 s for both the devices. Since such a large shift is not observed without GO layer, we consider that memory effect was due to electron trapping in GO. Further, retention of the initial memory window was measured to be 63% and 37% after 3000 s for PMMA and PVP based devices, respectively.     

Controlled surface doping for operating stability enhancement in organic field-effect transistors

The introduction of an inorganic/organic or organic/organic heterojunction in the pentacene-based organic field-effect transistors is demonstrated to be in favor of improving their operating stability. The heterojunction-induced p-type doping of pentacene is nondestructive, and it can be controlled by varying the adlayer thickness. The bias stress effects are compared at similar surface carrier density for the doped and undoped devices, and the current flow in the pentacene bulk is found to be more stable than that in the conducting channel close to the gate dielectric. In the initial stage of the bias stress characteristics, the carrier trapping associated with the gate dielectric is mainly responsible for the current instability. On the other hand, in the prolonged stage, the carrier trapping in the active layer may become dominant.