FPGA在CSR主环电源控制系统中的应用

论文介绍了基于DSP和FPGA主环电源控制系统的设计.DSP与DAC之间通过FPGA连接,并通过FPGA来控制DAC的输出.重点介绍FPGA的程序设计及其仿真结果.系统达到了设计要求,已成功应用于CSR主环控制系统.     

VME总线在线"从串模式"配置FPGA的设计与实现

本文介绍了在线配置FPGA硬件设计及工作原理.所设计的系统可以使FPGA的配置数据通过VME总线写入到一片Flash Memory中,并在加电时或使用命令的方式通过Flash Memory来配置FPGA.另外,FPGA的配置数据还可以直接保存在PC机终端上,而不是Flash Memory中,在需要时,通过VME总线直接将配置数据配置给FPGA.     

基于串行通信的远程FPGA在线配置

针对核电子学系统在高辐射等特殊环境中,不方便以常规方式进行FPGA器件逻辑数据更新的问题,介绍了一种利用PC机和CPLD,并基于长距离串行通信线路来实现的FPGA在线配置系统。并以ALTERA公司的CYCLONE系列FPGA和EPCS配置芯片为例,结合常用的AS配置模式,从原理、硬件连接、软件功能和通信协议等几个方面给出了该系统的详细设计。采用这种方法,我们可以在100 m距离同时配置多个FPGA,或者在150 m的距离配置单个FPGA。     

基于LabVIEW语言的PCI总线数据传输系统

介绍了一种基于LabVIEW的针对FPGA的数据开发接口平台。该系统核心硬件由FPGA组成,可提供数据处理、数据IO等多种功能,并通过PC104对外提供PCI接口实现通信。该系统可兼容NI(美国国家仪器公司)CRIO机箱。它不同于传统的用HDL语言对FPGA的开发流程,这样一个系统的所有软件代码,包括FPGA代码都可以由LabVIEW语言实现。借助于图形化的LabVIEW语言,它大大降低了实验人员对于FPGA的开发要求,是一种通用的数据处理和数据接口平台。给出了平台的结构组成,并着重介绍了平台数据传输部分的实现和测试。     

基于FPGA与单片机的γ剂量率仪的研制

研制了以FPGA为数据采集核心、单片机为数据处理器的多通道新的γ剂量率仅.文中介绍了FPGA与单片机的通信接口设计、FPGA设计的数据采集模块与功能仿真图和单片机软件和硬件设计框图.并对单片机部分软件设计进行了阐述.设计过程中最大限度的利用数字技术.经过测试,实现了较好的效果.     

基于FPGA的核电厂安全级仪控系统验证与确认

现场可编程门阵列(FPGA)设备因具有行为确定、结构简单、时间响应快、易于取得监管和取证等优点,越来越广泛应用于核安全系统,特别是新一代核电厂安全级仪控系统。FPGA安全级仪控产品可以克服核电仪控系统设备老化问题,是目前核电厂仪控系统进行技术改造的首选方案,满足三代核电高安全性与高可靠性的要求。同时,随着我国核电建设事业的快速发展及三代AP1000技术的引进,被誉为核电厂"神经系统"的数字化控制系统(DCS)的自主化越来越受到人们的关注。但是,核电业主和国家核安全管理当局都要求对FPGA安全级DCS系统进行严格的验证与确认(VV),以保证FPGA安全级DCS产品的高质量和高可靠性。论文探讨了基于FPGA技术的安全级DCS系统研发过程VV生命周期模型、VV标准体系、VV活动和方法,讨论了FPGA技术安全级DCS产品VV可能采用的仿真和测试技术,并提出了FPGA开发工具鉴定的方法。     

基于ARM与FPGA的运动控制平台研究

介绍了基于ARM与FPGA的实时束流截面测量的嵌入式平台,讨论了电机控制器子系统的硬件接口设计,通过ARM的外围总线实现了ARM与FPGA的接口,并采用Linux操作系统对FPGA设备进行驱动开发。自主开发的硬件接口板用于测试ARM与FPGA实现方案以及整机集成后的硬件性能。实验测试表明,硬件接口板能有效实现电动控制,原运动控制器定位精度为1μm,现平台定位精度达2μm,数量级上满足要求,可用于后续FEL设备升级。     

基于辐射回避的SRAM型FPGA瞬时电离辐射效应测试系统研制

介绍了瞬时电离辐射环境中SRAM型FPGA配置存储器测试的实现方法,提出了将辐射回避应用于FPGA瞬时电离辐射效应测试的方法,设计了可辐射回避的在线测试系统,并对FPGA进行了瞬时电离辐射效应实验。结果表明,测试系统能准确、可靠地进行配置存储器测试,辐射回避是实现大规模集成电路瞬时电离辐射效应测试的有效手段。     

嵌入式实时操作系统VxWorks在FPGA硬核（PowerPC405）中的移植研究

主要介绍了FPGA嵌入式硬核(PowexPC405)的特点和内核结构,并且详细阐述了在FPGA嵌入式硬核中移植VxWorks的方法并予以实现.     

基于SEM的FPGA抗单粒子翻转技术研究及验证

随着FPGA片内纠检错技术的发展,Xilinx公司在旗下的SRAM型FPGA上应用了一种名为软错误修复(SEM)的加固技术,大幅提升了配置RAM的单粒子软错误检测和修复效率。但这种片内加固技术本身需要使用一定的逻辑和存储资源,同样也有发生单粒子软错误的风险。本文分析了应用SEM加固技术的必要性和存在的问题,提出一套基于SEM的FPGA抗单粒子翻转解决方案,并给出了在XC7K410T型FPGA上的试验验证结果,验证了加固技术的有效性。     

Design of data transmission for a portable DAQ system

Field Programmable Gate Array （FPGA）, combined with ARM （Advanced RISC Machines） is increasingly employed in the portable data acquisition （DAQ） system for nuclear experiments to reduce the system volume and achieve powerful and multifunctional capacity. High-speed data transmission between FPGA and ARM is one of the most challenging issues for system implementation. In this paper, we propose a method to realize the high-speed data transmission by using the FPGA to acquire massive data from FEE （Front-end electronics） and send it to the ARM whilst the ARM to transmit the data to the remote computer through the TCP/IP protocol for later process. This paper mainly introduces the interface design of the high-speed transmission method between the FPGA and the ARM, the transmission logic of the FPGA, and the program design of the ARM. The theoretical research shows that the maximal transmission speed between the FPGA and the ARM through this way can reach 50 MB/s. In a realistic nuclear physics experiment, this portable DAQ system achieved 2.2 MB/s data acquisition speed.     

FPGA技术在核电厂保护系统中的应用

核电厂反应堆保护系统广泛采用CPU技术进行开发,使得保护系统中包含操作系统和应用软件等中间环节,增加了其出现共模故障的概率,降低了其可靠性和安全陛.通过比较FPGA（现场可编程逻辑门阵列）技术与CPU技术的差异,阐明采用FPGA技术开发保护系统的优势.在此基础上,提出了基于FPGA的反应堆保护系统的开发流程,总结了测试和验证过程中的注意事项,对新一代保护系统的设计及应用具有重要的参考价值.     

On the speed of response of an FPGA-based shutdown system in CANDU nuclear power plants

Several issues in an FPGA based implementation of shutdown systems in CANDU nuclear power plants have been investigated in this paper. A particular attention is on the response time of an FPGA implementation of safety shutdown systems in comparison with operating system based software solutions as in existing CANDU plants. The trip decision logic under “steam generator (SG) level low” condition has been examined in detail. The design and implementation of this logic on an FPGA platform have been carried out. The functionality tests are performed in a hardware-in-the-loop (HIL) environment by connecting the FPGA based system to an NPP simulator, and replacing one channel of Shutdown System Number 1 (SDS1) in the simulator by the FPGA implementation. The response time of the designed system is also measured through multiple tests under different conditions, and statistical data analysis has been performed. The results of the response time tests are compared against those of a software-based implementation of the same trip logic.     

基于NuPAC的核电厂反应堆保护系统

现场可编程门阵列（FPGA）技术作为一种不同于CPU技术的数字电子技术,越来越广泛地用于核电厂安全级仪控系统。本文介绍了基于FPGA技术的核电厂反应堆保护系统平台NuPAC及反应堆保护系统的结构,分析了NuPAC平台在简化系统设计、独立性和多样性等方面对反应堆保护系统结构的改进。此外,分析了FPGA技术在提升反应堆保护系统的确定性、安保性和可持续性等方面的优势,介绍了反应堆保护系统的需求分析及其挑战。本文将为今后国内其他基于FPGA技术的核安全级仪控系统的开发提供参考。     

An embedded single-board computer for BPM of SSRF

An embedded single-board computer (SBC) system based on AT91RM9200 was designed for monitoring and controlling the digital beam position monitor system of Shanghai Synchrotron Radiation Facility (SSRF) through the Virtex-4 FPGA in the digital processing board.The SBC transfers the configuration commands from the remote EPICS to the FPGA,and calculates the beam position data.The interface between the FPGA and the SBC is the Static Memory Controller (SMC) with a peak transfer speed of up to 349 Mbps.The 100 Mb Ethernet is used for data transfer between the EPICS and SBC board,and a serial port serves as monitoring the status of the embedded system.Test results indicate that the SBC board functions well.     

应用于同步加速器时序控制的片上可编程系统的设计

同步加速器对控制信号的时闻约束要求非常严格,时序控制是加速器控制系统中十分重要的环节.在兰州重离子加速器冷却储存环(HIRFL-CSR)控制系统中,时序控制主要采用FPGA+ARM+linux+DSP的体系结构.本文介绍基于FPGA和uClinux操作系统的片上可编程系统(SOPC)的设计,可将目前ARM+LINUX的工作完全集成在FPGA内实现,省去专用ARM芯片.其最高工作频率可达185 MHz,硬件资源消耗不到4%.片上可编程系统的硬件处理器系统和操作系统都可根据具体需求重新裁剪和配置.SOPC技术在加速器物理以及其他领域有着非常广泛的应用前景.     

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.     

A new high speed solution for the evaluation of Monte Carlo radiation transport computations

Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are large, expensive, and still not fast enough to make the Monte Carlo technique useful for calculations requiring a near real-time evaluation period. For Monte Carlo simulations, a small computational unit called a Field Programmable Gate Array (FPGA) is capable of bringing the power of a large cluster computer into any personal computer (PC). Because an FPGA is capable of executing Monte Carlo simulations with a high degree of parallelism, a simulation run on a large FPGA can be executed at a much higher rate than an equivalent simulation on a modern single-processor desktop PC. In this paper, a simple radiation transport problem involving moderate energy photons incident on a three-dimensional target is discussed. By comparing the evaluation speed of this transport problem on a large FPGA to the evaluation speed of the same transport problem using standard computing techniques, it is shown that it is possible to accelerate Monte Carlo computations significantly using FPGAs. In fact, we have found that our simple photon transport test case can be evaluated in excess of 650 times faster on a large FPGA than on a 3.2 GHz Pentium-4 desktop PC running MCNP5.