Nondestructive DCIV method to evaluate plasma charging damage inultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-Å gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N₂O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N₂O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides     

The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Improved immunity to plasma damage in ultrathin nitrided oxides[CMOS technology]

Plasma-induced damage in various 3-nm thick gate oxides (i.e., pure O₂ and N₂O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as at the wafer edge for pMOS devices, while it occurs only at the wafer center for nWOS devices. These interesting observations could be explained by the polarity dependence of ultrathin oxides in charge-to-breakdown measurements. Additionally, ultrathin N₂O-nitrided oxides show superior immunity to charging damage, especially for pMOS devices     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.     

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

Plasma-charging damage in ultra-thin gate oxide

The impact of plasma-charging damage on ultra-thin gate oxide is discussed. The argument for plasma-charging damage becoming less important is examined. Without considering the area and failure rate scaling effect, one mode of charging damage does become less important while other modes continue to be a serious problem. After scaling is properly accounted for, all charging damage remains a serious problem. The problem is more serious for thinner gate oxides because its life time becomes a limiting factor in device scaling. No one has yet made proper measurement for charging damage in the ultra-thin gate oxide regime. Stress-induced leakage current with properly designed tester may be used for ultra-thin gate-oxide damage measurement if one has the required sensitivity in the measurement. However, one must take care to use stress to reveal the latent defects that are hidden by annealing.     

A model and experiments for thin oxide damage from wafer chargingin magnetron plasmas

A physically based model that has been developed to explain the role of plasma nonuniformity in charge damage to oxides is presented. For a uniform plasma the local conduction currents to the water surface integrate to zero over the RF period, and the surface charging is sufficient to damage oxides. For the case of thin oxides under a gate exposed to a nonuniform magnetron plasma, the gate surface can charge up until the oxide tunneling current balances the difference in the mean local conduction currents from the plasma. It is this oxide current that leads to degradation. The oxide current obtained via SPICE circuit simulations, probe measurements and breakdown measurements shows good agreement with experimental damage data of `antenna' capacitors     

Sensitivity and limitations of plasma charging damage measurementsusing MOS capacitors structures

This work investigates the sensitivity and limitation of capacitor testing for measuring potential charging damage to gate oxides after a given plasma step. Ramp breakdown measurements are quick and easy to automate but lack sensitivity. Accelerated charge-to-breakdown measurements offers better sensitivity but with long measurement times. V-t measurements using the slope dV/dt after initial charging are found to be very sensitive to charge damage. The damage sensitivity of this method is high and involves tradeoffs between antenna ratio, testing current and testing time. All of which are critical to damage testing. Leakage measurements offers short measurement times and high sensitivity but are limited by the noise level of the measurement system and by the need to make good probe contact to the gate material     

Charging control on high energy implanters: A process requirement demonstrated by plasma damage monitoring

Charging phenomena is one of the main problems faced in ion implantation. Anti-charging system such as plasma flood gun (PFG) are currently running on high current and medium current implanters to reduce potential charging damage on device structures. However, in a conventional production line, high energy implantation steps are still often used without any charge compensation technique. Faced with micro-arcing defects detected after Well implantation steps on production lots, we have clearly demonstrated that the defectivity issue was eradicated by enabling the PFG system on the VIISta3000 high energy implanter. In addition we have investigated charging as a function of PFG properties by plasma damage monitoring (PDM) and proved that voltages developed on oxidized wafers processed on the VIISta3000 were not insignificant.     

等离子体工艺引起的MOSFET栅氧化层损伤

在深亚微米 MOS集成电路制造中 ,等离子体工艺已经成为主流工艺。而等离子体工艺引起的栅氧化层损伤也已经成为限制 MOS器件成品率和长期可靠性的一个重要因素。文中主要讨论了等离子体工艺引起的充电损伤、边缘损伤和表面不平坦引起的电子遮蔽效应的主要机理 ,并在此基础上讨论了减小等离子体损伤的有效方法。     

A comparison between plasma charging-damage and inductive-damage: Damage response to Fowler-Nordheim stress

This paper reports on the results of a study performed to compare the effects of charging damage and inductive damage to 0.5 μm n-channel MOSFETs arising from plasma etching at the gate-definition etch and metal-1 etch levels, respectively. The MOSFETs were fabricated on 200 mm p/p+ silicon wafers using a full CMOS process. The gate-definition etch step was performed using a chlorine-based chemistry and the metal etch step was done using a BCl₃/N₂/Cl₂ plasma. It is found that charging damage is electrically inactive after the full CMOS process flow; however, it is electrically activated by Fowler-Nordheim (F-N) stress when charging damage is clearly seen to correlate with the area of charging antenna in the device. Inductive damage, on the other hand, is seen to impact transistor parameters directly after the CMOS process and before the application of F-N stress. This is attributed to distinctly different mechanisms that are responsible for the creation of the two types of damage: charging damage arises from a dc current stress, whereas inductive damage is suggested to arise from ac current stress.     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

A New Technique for Measuring Gate-Oxide Leakage in Charging Protected MOSFETs

While accurate measurement of gate-oxide leakage in isolated CMOS oxides can be straightforward, it is not the case for CMOS oxides connected to a plasma-charging protection device. In this paper, a method enabling accurate gate-oxide leakage extraction from CMOS transistors directly connected to a gated MOSFET-based charging protection device is described. The method extracts gate-oxide leakage at the bottom side of the gate-oxide from the drain/source terminal of the protected MOSFETs biased into inversion while diverting the parasitic leakages from the protection device into a P⁺ tap sink. The location and design of the P⁺ tap sink play an important role on the success of the method. The method demonstrates a high measurement accuracy over the conventional method with a nearly 99% absorption efficiency of the protection-device-induced leakage by the P ⁺ tap sink, with the test structures used in this study. The method enables a saving of up to 30% of the layout space in the design of the charging test structures in test chips by eliminating usage of the fuse between the protected and protecting devices. A correlation study performed with the data measured by the new method and the conventional method suggests that both protected and protecting transistors can experience gate-oxide damage at the same time during back-end integrated circuit (IC) manufacturing process if the protected transistors violate the gate-charging design rules. It also indicates that the protected transistors have higher chance to receive more severe damage than the protecting transistors due to different oxide damage mechanisms associated with the terminal connectivity of these transistors