A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.     

Integrated complementary HBT microwave push-pull and Darlingtonamplifiers with p-n-p active loads

The authors report the microwave results of complementary heterojunction bipolar transistor (HBT) amplifiers that integrate both n-p-n and p-n-p devices on the same chip using selective molecular beam epitaxy (MBE). An HBT wideband amplifier utilizing the Darlington configuration and implementing a p-n-p active load has a gain of 7.5 dB and a bandwidth from DC to 2.5 GHz. A complementary push-pull amplifier has a saturated output power of 7.5 dBm at 2.5 GHz     

Theory and design of an ultra-linear square-law approximated LDMOSpower amplifier in class-AB operation

This paper describes a power amplifier, employing parallel-connected laterally diffused metal-oxide semiconductor (LDMOS) devices with optimized channel widths and bias offsets to approximate ideal square-law behavior of the overall transconductance in class-AB operation. The proposed method results in a significant linearity improvement over a large dynamic range in comparison to a conventional amplifier in class-A or class-AB operation. Measurements demonstrate an improvement of 20 dB in third-order intermodulation distortion and 10 dB in adjacent channel power ratio for wide-band code-division multiple access at 12-dB output power backoff from the 1-dB gain compression point. Consequently, this amplifier can be operated more toward the compression region with better linearity and drain efficiency compared to a conventional LDMOS power-amplifier design     

A 5.7–6.4GHz GaAs HBT Power Amplifier with a Gain Enhanced Bias Circuit

This paper describes the design of a 5.7–6.4GHz GaAs Heterojunction bipolar transistor (HBT) power amplifier for broadband wireless application such as wireless metropolitan area networks. A bias circuit is proposed which enhances the power gain and provides a good linearity. Using the wideband matching network tech-niques with trap circuits embedded to filter the harmonics and the diode-based linearizing techniques, a broadband power amplifier module was obtained which exhibited a gain above 28dB. This is about 1dB improvement com-pared with those normal bias circuits at a supply volt-age of 5V in the frequency range of 5.7–6.4GHz, measured with Continuous wave(CW) signals. The saturated output power was greater than 33dBm in 5.7–6.4GHz and the out-put 1dB compression point was greater than 31dBm. The phase deviation was less than 5 degrees when the output power below 33dBm. The second and third order harmonic components were also less than -45dBc and -50dBc.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

应用于WiFi6的新型高线性度功率放大器设计

针对WiFi 6的设备需求,设计了一款工作在5.15 GHz～5.85 GHz的高线性度砷化镓异质结双极型晶体管射频功率放大器。为了保证大信号和高温下功率管静态工作点的稳定性,采用了一种新型有源自适应偏置电路。对射频功率检测电路进行了设计和改进,有效降低了射频系统的功耗。针对各次谐波分量产生的影响,对输出匹配网络进行了优化。仿真结果表明：该射频功率放大器芯片小信号增益达到了32.6 dB;在中心频率5.5 GHz时1 dB压缩点功率为30.4 dBm,功率附加效率超过27.9%;输出功率为26 dBm时,三阶交调失真低于-40 dBc。实测数据表明：小信号增益大于31.4 dB;5.5 GHz时1 dB压缩点功率为29.06 dBm;输出功率为26 dBm时,三阶交调失真低于-30 dBc。当输出功率为20 dBm时,二次三次谐波抑制到-30 dBc和-45 dBc。     

A gallium-nitride push-pull microwave power amplifier

A highly efficient linear, broad-band AlGaN-GaN high electron-mobility transistor (HEMT) push-pull microwave power amplifier has been achieved using discrete devices. Instrumental was a low-loss planar three-coupled-line balun with integrated biasing. Using two 1.5-mm GaN HEMTs, a push-pull amplifier yielded 42% power-added efficiency with 28.5-dBm input power at 5.2 GHz, and a 3-dB bandwidth of 4-8.5 GHz was achieved with class-B bias. The output power at 3-dB gain compression was 36 dBm under continuous-wave operation. Along with the high efficiency, good linearity was obtained compared to single-ended operation. The second harmonic content of the amplifier was more than 30 dB down over the 4-8.5-GHz band, and a two-tone excitation measurement gave an input third-order intercept point of 31.5 dBm at 8 GHz. These experimental results and an analysis of the periodic load presented by the output balun suggest the plausibility of broad-band push-pull operation for microwave systems with frequency diversity.     

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.     

Monolithic integration of complementary HBTs by selective MOVPE

The monolithic integration of n-p-n and p-n-p heterojunction bipolar transistors (HBTs) through the use of selective metal organic vapor phase epitaxial regrowth is discussed. This was accomplished by masking, patterning, and etching a p-n-p HBT wafer and then selectively regrowing an n-p-n structure in the etched areas. The selective epitaxial regrowth did not degrade the current gain of the p-n-p structure. Several complementary amplifier circuits were fabricated and tested successfully, demonstrating the feasibility of a monolithic complementary HBT technology     

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.     

基于GaN器件的连续型高效宽带功率放大器设计*

提出一种高效宽带功率放大器的设计方法,并基于GaN HEMT 器件CGH40010F 设计了验证电路。利用功放管输出寄生参数的等效网络,将基于连续型功放理论得到的负载阻抗转换到封装参考面上,并利用多谐波双向牵引技术对转换后的负载阻抗进行适当调整,使二次谐波负载阻抗位于高效率区以及基频负载阻抗能够获得高功率附加效率和高输出功率。谐波阻抗位于高效率区使得匹配网络的设计简化为基频匹配网络的设计,降低了对谐波阻抗匹配的难度和宽带匹配网络设计的复杂度。实验结果表明:在1GHz -3GHz 工作频带(相对带宽100%)内,功率附加效率在53%-64.6%之间,输出功率为39.5±2dBm,增益为11.5±2dB,二次谐波小于-15dBc,三次谐波小于-25dBc。     

A New Design of Doherty Amplifiers Using Defected Ground Structure

In this letter, a new Doherty power amplifier having the ideal harmonic termination condition that has been usually ignored is proposed. A defected ground structure (DGS) is adopted on the ground pattern of the output lambda/4 impedance inverter of the carrier amplifier and output offset transmission line of the peaking amplifier that are essential for proper load modulation operation of a conventional Doherty amplifier. As a result of the second and third harmonic termination, excellent improvement in power added efficiency (PAE), gain, maximum output power as well as linearity is obtained. The acquired improvements in gain, maximum output power (P_{1 dB}), PAE, and adjacent channel leakage ratio to wideband code division multiple access 2FA signal are 0.33 dB, 0.42 dB, 12.7%, and 5.1 dB, respectively. Moreover, physical length of microstrip line is shortened fairly by DGS, therefore the whole amplifier circuit size is considerably reduced     

Low-harmonic distortion in single-ended and push-pull class E power amplifier by using slotted microstrip lines

In this work, a very low-harmonic distortion with high power-added efficiency (PAE) power amplifier (PA) with slotted microstrip lines is reported. The circuit is a push-pull class E amplifier, terminated with defected structures to improve the spectrum purity and efficiency. The relationship of the second and third harmonic to the fundamental is 70 and 54 dBc, respectively. The amplifier is developed with HBT medium power transistors. The circuit works at 1.8 GHz obtaining a PAE close to 60%, delivering an output power of 24 dBm with a power gain of 13.3 dB.     

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.     

UHF宽带线性功率放大器设计

针对电磁环境模拟器应用设计了一个全固态UHF波段多级宽带线性高功率放大器。驱动放大器工作在A类，末级放大器以三个AB类功放模块频域分段覆盖工作频段，通过控制PIN开关切换。末级输出接低通滤波器改善谐波。实测从400MHz～1250MHz，功放的1dB压缩点功率为25W（44dBm），二次谐波低于-40dBc，输出功率在38dBm时双音测试三阶交调（IM3）优于-44dBc。     

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.     

L频段低谐波失真功率放大器的设计

针对L频段低谐波失真功率放大器的设计,进行线性与非线性电路分析仿真和电路的优化设计。从理论上分析了甲乙类功率放大器的谐波失真特性,通过采用具有抑制谐波特性的输出匹配电路以降低功放产生的谐波失真。测试得到电路的关键技术指标为:工作频率范围1 390~1 510MHz,增益35 dB,1 dB压缩点33 dBm,并获得了满意的谐波抑制指标,在1 480 MHz、输出功率33dBm时,二、三次谐波分别为-70 dBc和-63 dBc。结果表明在功放设计中,优化设计输出匹配电路可以有效抑制功放的谐波失真。     

Linearity optimization of a high power Doherty amplifier based on post-distortion compensation

The linearity of a 30-W high-power Doherty amplifier is optimized using post-distortion compensation. A balanced high-power Doherty amplifier using two push-pull laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) is linearized by optimum adjustment of the peaking compensation line, shunt capacitors, and gate biases. The measured results of an optimized Doherty amplifier for a four-carrier wideband code division multiple access (W-CDMA) signal, achieved -43 dBc adjacent channel leakage ratio (ACLR) at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2dB and 6.5dB in comparison to the Doherty amplifier before optimization and a ClassAB amplifier, respectively.     

High-Gain 15-W Monolithic Power Amplifier with Internal Fault Protection

A combination of circuit and device innovations has resulted in the development of a 15-W integrated-circuit power amplifier that incorporates a preamplifier on the same chip to give an overall closed-loop gain of 60 dB. Two novel devices used are a new high-frequency drift-lateral p-n-p to improve stability and a new 3-A n-p-n power transistor design with individual emitter ballasting to achieve a larger safe-operating area. Other interesting features are an externally adjustable short-circuit current limit, a built-in thermal shutdown circuit that automatically limits the junction temperature to 175/spl deg/C, an electronic shutdown control to mute the amplifier; a supply voltage range of 10-40 V, excellent power-supply rejection (55 dB), and a unique biasing technique that ensures that the output quiescent point remains at one-half the supply voltage with the total bias current changing only 3 mA over the complete supply voltage range (10-40 V).     

A low-distortion K-band GaAs power FET

A K-band low-distortion GaAs power MESFET was developed by incorporating a pulse-type channel doping profile using molecular-beam-epitaxial technology and a novel 0.3-μm T-shaped gate. The low-distortion FETs offer about 10 to 15 dBc improvement in second-harmonic distortion compared to devices fabricated on a uniformity doped active layer. Significantly larger power load-pull contours are obtained with the low-distortion devices, indicating the improved linearity of these devices. In an 8-20-GHz single-stage broad-band amplifier, up to 10 dBc improvement in harmonic performance was achieved using the low-distortion device. This low-distortion device exhibits very linear transconductance as a function of the gate bias. A typical 750-μm-gate-width device is capable of 26 dBm of output power with 6 dB of gain, and power-added efficiency in excess of 35% when measured at 18 GHz. At 25 GHz, the device is capable of 24 dBm of output power with 5 dB associated gain