IC测试原理-射频/无线芯片测试基础

1 引言 芯片测试原理讨论在芯片开发和生产过程中芯片测试的基本原理,一共分为四章,下面将要介绍的是最后一章.第一章介绍了芯片测试的基本原理,第二章介绍了这些基本原理在存储器和逻辑芯片的测试中的应用,第三章介绍了混合信号芯片的测试.本文将介绍射频/无线芯片的测试.     

深入系统芯片的量产验证

随着集成电路技术日新月异的发展,使得单块芯片的集成度越来越高,将复杂系统集成于一个独立的系统芯片(System-On-a-Chip,SOC)成为经济可行的方案。系统芯片较以前的电路板系统在重量、体积、性能和价格等方面都具有优势。然而由于测试生成时间约与电路规模成三次方正比,系统芯片设计者若在设计前忽略测试问题,待产品大量生产时甚至会出现测试代价超过制造代价的窘迫情形。因此,测试问题将是SOC发展的一大挑战。本文将探讨SOC测试问题与目前的一些解决方案。请注意本文所指的测试(Testing)是检测产品大量生产时是否有缺陷(defects),而非验证(verification)芯片设计是否正确。     

IC测试原理-芯片测试原理

1引言 芯片测试原理讨论在芯片开发和生产过程中芯片测试的基本原理,一共分为四章,下面将要介绍的是第二章.我们在第一章介绍了芯片测试的基本原理;第二章讨论了怎么把这些基本原理应用到存储器和逻辑芯片的测试上;本文主要介绍混合信号芯片的测试;接下来的第四章将会介绍射频/无线芯片的测试.     

环氧塑封料十年成长

中国半导体产业经过多年的发展,已初步形成了设计、芯片制造及封装测试三业并存、相互协调发展格局.国内从事电子封装生产、科研、教学等单位300余家,从业人数达到110万人以上.随着芯片集成度的极大提高,高端封装产品的技术含量日增,封装测试成本在集成电路成本中占比重加大,多年来封装业的销售额一直在半导体设计、芯片制造及封装测试三业中占50％以上,2011年半导体封装业的销售额为975.7亿元.     

利用先进技术降低开发和生产成本

当今的半导体制造商在生产规模和功能上都有空前复杂的芯片。为了加快量产步伐，缩短测试时间，降低测试成本，这些芯片正从各个方面挑战着传统的芯片测试方法。为了应对这些挑战，制造商们正在努力寻求一种更加有效的方法，以流畅设计到测试的转换，加速产品的验证和特性分析，高效低成本地进行产品测试。     

芯片尺寸封装之高压蒸煮可靠度实验破坏机构分析

主要是研究湿气敏感可靠度的破坏机制.在高压蒸煮(PCT)条件(121.C,2atm,100RH%,and 1 68hrs)下的测试.相关材料如封装树酯吸湿及芯片背面特性的影响.     

电压检测芯片失效分析

近年来,随着智能电表的广泛使用,其质量和可靠性问题受到了人们越来越多的关注.但是,由于各种原因,产品投入市场后仍会出现各种失效现象.因此,对某智能电表的电压检测芯片的失效现象进行了分析,通过外观检查、 电参数测试和X-射线测试等手段找到了该芯片的失效原因,并针对发现的问题提出了相应的改进意见.     

英特尔大连芯片厂将采用65纳米制程技术

英特尔公司近日宣布,正在建设中的大连芯片厂（Fab68）将采用65纳米制程技术,这座全新的300毫米晶圆厂在2010年建成投产后,将生产制造先进的芯片组产品。大连芯片厂总经理柯必杰表示：“大连芯片厂的建设没有受到全球经济衰退的影响,工厂将于2010年如期建成投产。     

DA测试公司应用科利登Quartet One来提高测试能力

美国加州,弗里蒙特,2003年4月8日科利登系统公司(在纳斯达克挂牌为CMOS)为世界各地的芯片生产商提供“从设计到生产”测试方案,并在该领域具有领先地位。该公司于今日宣布DA测试公司已起用该公司产品QuartetOne进行SoC芯片测试,其中包括测试程序开发,品质鉴定以及生产测试。位于加拿大,安大略湖的DA测试公司是一家提供全面测试业务的公司,该公司将应用科利登公司的QuartetOne提高其芯片测试能力,特别是对于一些大产量器件的测试,包括消费类电子产品,通信电子器件和计算机芯片等。DA测试公司之所以选用QuartetOne是因为该系统能广泛…     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

圆片清洗过程中静电控制

随着半导体技术的不断发展,对集成电路封装过程中的静电控制要求也越来越高。传统清洗机清洗圆片时,通常会产生大量的静电电压,可能引起芯片失效、损伤造成漏电流增大从而导致电路的损坏。如何降低清洗机清洗圆片时产生的静电电压,对减少封装过程中因ESD引起的芯片失效有着比较重要的意义。为此我们利用高压喷雾旋转清洗机针对圆片清洗这个步骤进行了一系列的试验。文中涉及控制清洗液的电阻率,并尝试改变清洗过程中的相关清洗条件,最终达到封装过程中要求的±200V的静电控制要求。     

单片机的ESD EMP效应及加固技术研究

ESD EMP(静电放电产生的电磁脉冲)具有上升沿陡、频带宽和峰值大等特点,对电子系统具有很强的干扰和破坏作用。为研究ESD EMP对电子系统的影响,以单片机为实验对象,对单片机系统进行了ESD EMP辐照效应实验。实验表明,单片机系统在ESD EMP作用下,会出现10多种故障现象。文中在实验基础上研究了单片机加固技术。     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

We have thoroughly investigated the advantages of a silicon through-via (STV) interconnection in decreasing the inductive impedance of a power distribution network (PDN) and suppressing simultaneous switching noise (SSN) in a 3-D stacked chip package. A double-stacked chip package with STV interconnections was fabricated and measured together with a similar double-stacked chip package with conventional bonding-wire interconnections. We successfully demonstrated that significant reduction of the inductive PDN impedance, from 1.66 nH to 0.79 nH, can be achieved by replacing the conventional bonding wires in the multiple-stacked chip package by STV interconnections. Furthermore, we have shown that the STV interconnections can considerably reduce high-frequency SSN, by more than 80%, compared to the conventional bonding-wire interconnections.     

A single-chip fingerprint sensor and identifier

A chip architecture that integrates a fingerprint sensor and an identifier in a single chip is proposed. The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. The sensing element is built above the processing element in each pixel. The chip architecture realizes a wide-area sensor without a large increase of chip size and ensures high sensor sensitivity while maintaining a high image density. The sensing element is covered with a hard film to prevent physical and chemical degradation and surrounded by a ground wall to shield it. The wall is also exposed on the chip surface to protect against damage by electrostatic discharges from the finger contacting the chip. A 15×15 mm² single-chip fingerprint sensor/identifier LSI was fabricated using 0.5-μm standard CMOS with the sensor process. The sensor area is 10.1×13.5 mm². The sensing and identification time is 102 ms with power consumption of 8.8 mW at 3.3 V. Five hundred tests confirmed a stranger-rejection rate of the chip of more than 99% and a user-rejection rate of less than 1%     

中功率感性负载直流电流检测及其应用

为找到一种简单、高效的中功率直流感性负载电流检测电路,文中描述了几种方案,并对其进行了比较和验证,最终选出一种较为适合的方案,且举例说明其应用领域及具体实现方式。所述方案选用美信公司的MAX9918芯片,这是一种单电源供电、高精度电流型放大器,具有较高地输入共模范围,可扩展至-20 ~+75 V。该款放大器适用于直流电机和螺线管等感性负载的电流检测。     

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.     

静电损伤及其防护措施

本文提出了轻微静电损伤和严重静电损伤的概念,简述了静电放电模型,指出了提高器件抗静电放电能力的对策。     

3.4GHz频率的S波段SAW滤波器

该文研制了一款频率3.4 GHz的S波段声表面波(SAW)滤波器。该滤波器采用一种由新型谐振器构成的阻抗元结构,能提升抗热释电静电损伤能力,用时可在一定程度上提升器件的功率承受能力。同时研制了尺寸为2.0 mm×1.6 mm的芯片级封装(CSP)基板。采用倒装焊工艺实现了芯片与CSP基板的电连接,降低了电磁寄生影响。结果表明,研制的SAW滤波器频率为3.408 GHz,插损为2.23 dB,8 GHz远端阻带大于30 dB,且实测的功率承受能力达到30 dBm。     

Complete System for Wireless Powering and Remote Control of Electrostatic Actuators by Inductive Coupling

This paper proposes a successful asynchronous remote powering and control of electrostatic microactuators, organized in two distributed micro motion systems (DMMS) with the aim of realizing a wireless microrobot. Remote powering of the integrated circuit (IC) and the microelectromechanical systems (MEMS) components is obtained by inductive coupling at 13.56 MHz, and the digital transmission is created by modulating the carrier amplitude by 25%. The system includes a high-voltage controller IC. It provides a link between the power and data on the receiver antenna on one side, and the actuators of the microrobot on the other. The micromachined antenna is designed to optimize the inductive coupling. The main IC building blocks, such as the received signal rectifier/amplifier, the integrated digital processing and the DMMS actuation voltage generation are given in detail. The demonstrator has successfully achieved the remote control and asynchronous operation under 100 V of two arrays of 1700 electrostatic actuators, having a capacity of 2 nF each