倒装焊器件的密封技术

倒装焊的底部填充属非气密性封装,并且受倒装焊凸点焊料熔点、底部填充有机材料耐温限制,使得倒装焊器件的密封结构设计和工艺设计受限。文章结合气密性器件使用要求,设计了两种不改变现行倒装焊器件制造工艺、器件总体结构[3]的密封技术,经过分析论证以及工艺实验,确认其是可行的。密封的器件能够满足MIL-883G中有关气密性、内部水汽含量、耐腐蚀(盐雾)、耐湿以及机械试验等[6~7],密封结构、密封工艺均是在现有封装工艺条件基础上进行,具有非常强的可行性。     

基于倒装焊芯片的功率型LED热特性分析

对LED的导散热理论进行了研究,推导出了倒装焊LED芯片结温与封装材料热传导系数之间的关系。通过分析倒装焊LED的焊球材料、衬底粘结材料和芯片内部热沉材料对芯片结温的影响,表明衬底粘结材料对LED的结温影响最大,并且封装材料热传导系数的变化率与封装结构的传热厚度成反比,与传热面积成正比。该研究为倒装焊LED封装结构和材料的设计提供了理论支持。     

GaN基功率型LED芯片散热性能测试与分析

与正装LED相比,倒装焊芯片技术在功率型LED的散热方面具有潜在的优势.对各种正装和倒装焊功率型LED芯片的表面温度分布进行了直接测试,对其散热性能进行了分析.研究表明,焊接层的材料、焊接接触面的面积和焊接层的质量是制约倒装焊LED芯片散热能力的主要因素;而对于正装LED芯片,由于工艺简单,减少了中间热沉,通过结构的优化,工艺的改进,完全可以达到与倒装焊LED芯片相同的散热能力.     

气密性陶瓷封装PIND失效分析及解决方案

气密性陶瓷封装腔体内的自由粒子会严重影响到器件的可靠性。减少封装腔体内自由粒子数量,提高PIND合格率是气密性封装的主要技术之一。文章就陶瓷外壳封装集成电路PIND失效进行了分析,指出其主要原因,如外壳内部有瓷颗粒、芯片边缘未脱落的硅碴(屑)、芯片边沿的粘接材料卷起、脱落的粘接材料碎片、键合丝(或尾丝)、悬伸的合金焊料、封帽飞溅的合金焊料、平行缝焊打火飞溅的焊屑等,并提出了在封装工艺过程中如何对可能产生自由粒子的因素采取有效预防措施。最终使电路的粒子碰撞噪声检测合格品率达到98%以上,达到实际应用要求。     

塑封倒装焊器件DPA试验流程研究

倒装焊器件与常规的引线键合结构不同,现行的DPA标准不能完全适用于倒装焊结构.结合现有标准和倒装焊器件结构特点,以某塑封倒装焊集成电路器件为例,提出一套经过试验验证的、实用性强的倒装焊器件DPA试验流程.在原来标准的基础上提出了对BGA焊球材料成分分析、底充胶检查的超声扫描要求、芯片凸点结构检查等一些新的DPA要求.BGA焊球材料成分分析是使用能谱分析实现的,而芯片凸点结构检查则是通过对器件进行研磨开封实现的.经过试验验证,该流程方案可用于倒装焊集成电路器件的实际DPA工作.     

基于TSV倒装焊与芯片叠层的高密度组装及封装技术

系统级封装（Si P）及微系统技术能够在有限空间内实现更高密度、更多功能集成,是满足宇航、武器装备等高端领域电子器件小型化、高性能、高可靠需求的关键技术。重点阐述了基于硅通孔（TSV）转接板的倒装焊立体组装及其过程质量控制、基于键合工艺的芯片叠层、基于倒装焊的双通道散热封装等高密度模块涉及的组装及封装技术,同时对利用TSV转接板实现多芯片倒装焊的模组化、一体化集成方案进行了研究。基于以上技术实现了信息处理Si P模块的高密度、气密性封装,以及满足多倒装芯片散热与CMOS图像传感器（CIS）采光需求的双面三腔体微系统模块封装。     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

最新微电子器件封装技术研究

介绍了微电子封装中丝焊、倒装焊和无铅焊料技术的最新进展。分析了用于先进和复杂应用场合的堆叠芯片丝焊、低k超细间距器件丝焊以及铜丝焊技术。     

喷射下填充--一种新的下填充技术

<正> 1 引言 下填充,就是在倒装焊接装片的芯片下面,或在焊球(或焊柱)组装安装器件的管壳下面填充粘接剂,用以把芯片与封装外壳基板、或封装外壳基板与组装的印制板粘接起来,从而使它们之间由于热膨胀失配产生的集中在芯片与封装外壳、或封装外壳基片与组装印制板间焊料连接点的热应     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件(3D-MCM).采用层压、开槽等工艺获得埋置式高密度多层有机(FR-4)基板,通过板上芯片(COB)、板上倒装芯片(FCOB)、球栅阵列(BGA)等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术(SMT)兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成r融合多种互连方式3D-MCM封装结构.埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题.对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性.电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

An investigation of thermal enhancement on flip chip plastic BGApackages using CFD tool

This paper demonstrates the advantage of applying Predictive Engineering in the thermal assessment of a 279 inputs/outputs (I/Os), six-layer, depopulated array flip chip PBGA package. Thermal simulation was conducted using a computational fluid dynamics (CFD) tool to analyze the heat transfer and fluid flow in a free convection environment. This study first describes the modeling techniques on a multilayer substrate, thermal vias, solder bumps, and printed circuit board (PCB). For a flip chip package without any thermal enhancement, more than 90% of the total power was conducted from the front surface of the die through the solder ball interconnects to the substrate, then to the board. To enhance the thermal performance of the package, the heat transfer area from the backside of the die needs to increase dramatically. Several thermal enhancing techniques were examined. These methods included a copper heat spreader with various thicknesses and with thermal pads, metallic lid, overmolded with and without a heat spreader, and with heat sink. An aluminum lid and a heat sink gave the best improvement; followed by a heat spreader with thermal pads. Both methods reduced thermal resistance by an average of 50%. Detailed analyses on heat flow projections are discussed     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

The influence of Sn–Cu–Ni(Au) and Sn–Au intermetallic compounds on the solder joint reliability of flip chips on low temperature co-fired ceramic substrates

The formation of intermetallic compounds in the solder joint of a flip chip or chip scale package depends on the under bump metallurgy (UBM), the substrate top surface metallisation, the solder alloy and the application conditions. To evaluate the influence of intermetallic compounds on the solder joint reliability, a detailed study on the influence of the UBM, the gold finish thickness of the substrate top surface metallisation, the solder alloy and the aging conditions has been conducted. Flip chips bumped with different solder alloys were reflow-mounted on low temperature co-fired ceramic substrates. The flip chip package was then aged at high temperature and a bump shear test followed to examine the shear strength of the solder joint at certain aging intervals. It was found that the type of UBM has a great impact on the solder joint reliability. With Ni(P)/Au as the UBM, well-documented gold embrittlement was observed when the gold concentration in the eutectic SnPb solder was about 3 wt%. When Al/Ni(V)/Cu was used as the UBM, the solder joint reliability was substantially improved. Copper dissolution from the UBM into the solder gives different intermetallic formations compared to Ni(P)/Au as UBM. The addition of a small amount of copper in the solder alloy changed the mechanical property of the intermetallic compound, which is attributed to the formation of Sn–Cu–Ni(Au) intermetallic compounds. This could be used in solving the problem of the AuSn₄ embrittlement. The formation and the influence of this Sn–Cu–Ni(Au) intermetallic phase are discussed. The gold concentration in the solder joint plays a role in the formation of intermetallic compounds and consequently the solder joint reliability, especially for the Sn–Ag–Cu soldered flip chip package.     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput