共查询到20条相似文献,搜索用时 812 毫秒
1.
Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively. 相似文献
2.
Inhwa Jung Gunok Jung Janghoon Song Moo-Young Kim Junyoung Park Sung Bae Park Chulwoo Kim 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(2):116-120
Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mum CMOS technology occupies only 0.004 mm 2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a plusmn 2% phase error having one-cycle lock time. 相似文献
3.
Bo Ye 《Microelectronics Journal》2010,41(7):411-416
This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles. 相似文献
4.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(11):850-854
5.
Daeyun Shim Dong-Yun Lee Sanghun Jung Chang-Hyun Kim Wonchan Kim 《Solid-State Circuits, IEEE Journal of》1999,34(4):484-493
An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-μm double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1×0.7 mm2 . An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps±200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input 相似文献
6.
Lan-Chou Cho Chihun Lee Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2007,42(6):1261-1270
A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency 相似文献
7.
Yamaguchi K. Fukaishi M. Sakamoto T. Akiyama N. Nakamura K. 《Solid-State Circuits, IEEE Journal of》2001,36(11):1666-1672
An accurate yet simple multiphase clock generator has been developed by using a delay compensation technique based on phase interpolation that supplies a multiphase clock signal without increasing local circuit area. This generator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s×8-channel receiver fabricated with 0.13-μm CMOS technology. The four-phase generator in the receiver consumes 30 mW and occupies only 0.009 mm2. It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within ±5 相似文献
8.
Yongsam Moon Jongsang Choi Kyeongho Lee Deog-Kyoon Jeong Min-Kyu Kim 《Solid-State Circuits, IEEE Journal of》2000,35(3):377-384
This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm2) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7] 相似文献
9.
Kuo-Hsing Cheng Yu-Lung Lo 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(7):561-565
This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs. 相似文献
10.
《Solid-State Circuits, IEEE Journal of》2009,44(9):2478-2487
11.
Hyung-Gu Park SoYoung Kim Kang-Yoon Lee 《Analog Integrated Circuits and Signal Processing》2013,74(2):355-364
This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V. 相似文献
12.
Jang Y.-C. Bae J.-H. Park H.-J. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(10):1063-1067
A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 plusmn 0.4%. The chip was fabricated by using a 0.25-mum CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mumtimes250 mum and 18 mW at an input clock frequency of 1.0 GHz, respectively 相似文献
13.
Hyoung-Kook Kim Laung-Terng Wang Yu-Liang Wu Wen-Ben Jone 《Journal of Electronic Testing》2013,29(1):49-72
This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface. 相似文献
14.
15.
A novel Force/Release technique is proposed to eliminate the harmonic locking issue, which occurs in wide-range operation of Delay Locked Loops (DLLs). The proposed technique does not require replica delay line or multiphase clocks for frequency estimation, and hence, reduces the chip area and power consumption. Moreover, it can be employed, without modifications, to any type of the delay line controller. In addition, an area efficient technique for multi-bit Successive Approximation Register (SAR) DLL is proposed. A complete All-Digital DLL (ADDLL) design implementing the proposed Force/Release technique and the proposed 2-bit SAR scheme is developed. All design units are fully digital, described in Verilog and mapped to silicon using the IBM 0.13 μm Artisan standard cell library. The proposed design has an active area of 0.014 mm2 and can operate from 110 MHz to 1 GHz with a fixed latency of one clock cycle. It locks in 12 clock cycles and has a closed loop characteristics. 相似文献
16.
Chan-Hong Park Ook Kim Beomsup Kim 《Solid-State Circuits, IEEE Journal of》2001,36(5):777-783
This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply 相似文献
17.
Jonghoon Kim Dong Gun Kam Pil Jung Jun Joungho Kim 《Electromagnetic Compatibility, IEEE Transactions on》2005,47(4):908-920
In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz. 相似文献
18.
Xuefeng Yu Dai F.F. Irwin J.D. Jaeger R.C. 《Solid-State Circuits, IEEE Journal of》2008,43(6):1384-1393
This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm2. The chip was measured in packaged prototypes using 48-pin ceramic LCC packages. 相似文献
19.
《IEEE transactions on circuits and systems. I, Regular papers》2009,56(6):1102-1114
20.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2077-2082
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$ CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$ and has a peak-to-peak jitter of$pm $ 6.6 ps at 1.3 GHz. 相似文献