3D-MCM的X射线检测分析

X射线检测技术是一种能对不可视部位进行检测的技术。本文利用X射线对3D—MCM中的BGA焊点、基板和隔板之间的焊料凸点、叠层基板间的垂直互连和陶瓷-金属封装等进行检测;对存在于焊点和凸点中的气孔、垂直互连中的开路和封装中的孔洞等进行了分析。     

Void Evolution in Sub-100-Micron Sn-Ag Solder Bumps during Multi-reflow and Aging and its Effects on Bonding Reliability

The evolution of voids in the interfacial region of electroplated Sn-3.0Ag solder bumps on electroplated Cu and its effects on bonding reliability were studied. Results show that volume shrinkage resulted in void formation during multi-reflow, while the Kirkendall effect led to void formation during aging. A thick η-phase and voids at the boundaries among Cu₆Sn₅ grains promoted the void growth in the ε-phase. Though the formation of voids had a trivial weakening effect on the shear strength of the solder joints, the voids were a threat to the bonding reliability of solder bumps.     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Thermal and mechanical effects of voids within flip chip soldering in LED packages

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree.     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

贴片电阻焊点内部空洞缺陷自适应检测

贴片电阻在回流焊过程中,受工艺影响,焊点内部或多或少会存在空洞缺陷,空洞占比率过高会严重降低器件的可靠性。该文融合局部预拟合(LPF)活动轮廓模型和自适应圆形卷积核,提出一种贴片电阻焊点内部空洞缺陷自适应检测方法。首先,根据贴片电阻图像具有明暗两个明显区域的特点,通过求解区域平均灰度差异最大的优化问题将其自适应地分为较暗和较亮两个区域。然后,针对较暗区域中空洞与背景之间对比度低、空洞分布较稀疏、面积偏大等特点,采用局部预拟合活动轮廓模型进行空洞检测;针对较亮区域中空洞与背景之间差异明显、空洞分布密集、面积偏小等特点,提出一种自适应圆形卷积核检测空洞。最后,采用形状因子和平均灰度策略剔除误检测,实现贴片电阻焊点内部空洞精细检测。实验结果表明,该文算法相较于其他检测算法性能有明显的提升,平均Dice系数高达0.8846。     

Effect of Selected Process Parameters on Durability and Defects in Surface-Mount Assemblies for Portable Electronics

This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead-free (Pb-free) solder joints. An experiment was designed to systematically vary the printing and reflow process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with X-ray, to identify different types of defects, especially voids, and then test for electrical performance. The specimens were subjected to an accelerated thermal cycling test to characterize the durability of these error-seeded specimens and to study the effect of each manufacturing variable on the durability of the solder joints. The response variables for the design of experiments are thermal cycling durability of the solder joints and void area percentage in ball grid array (BGA) solder joints. Pretest microstructural analysis showed that specimens produced under inadequate reflow profiles suffered from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variables shows that waiting time, heating ramp, peak temperature, and cooling rate have nonlinear effects on thermal cycling durability. Two variables in particular [peak temperature and waiting time (the time waited after the solder paste barrel was opened and before print)] appear to have optimum values within the ranges investigated. Statistical analysis of void percentage area for all design of experiment (DOE) runs show that higher stencil thickness results in higher void percentage and that void percentage increases as time above melt and peak temperature increases.     

Effect of voids on thermo-mechanical reliability of chip resistor solder joints: Experiment,modelling and simulation

With the introduction of lead-free solder alloys, the effect of voids on solder joint reliability has rapidly gained importance. In this study, a first analysis of X-rayed CR0805 solder joints shows a significant reduction in void content, from 20% down to 2.5%, after vacuum soldering. The statistical analysis of the void distribution demonstrates that the vacuum option reduces number of voids and median diameter of voids in comparison to the convection soldering process. A subsequent accelerated thermal cycling test of these analysed test vehicles, according to JESD22-A104D, indicates the tendency of a higher characteristic life time for higher void content. In contrast to these findings, the 1% to failure criterion reveals a higher reliability for lower voiding. During the finite element method (FEM) modelling part of this study, two modelling approaches of void implementation into solder joint geometry are investigated: modelling with a constant volume of the standoff for different void contents, and a modelling approach with a random combination of void content and volume of standoff. The modelling approach with the random combination reveals that voids can reduce the lifetime in the “worst case” parameter combination. In particular, the 1% time to failure rate indicates a quantitative correlation with the experimental results. Furthermore, the FEM results suggest a higher impact on reliability for a single void in comparison to a distribution of multiple voids with similar void content. Finally, the FEM study shows a high sensitivity of predicted life time with respect to the standoff height. Based on this finding, the CR0805 solder joint geometry is examined using optical inspection and cross-section polishes with the outcome that the better wetting behaviour during vacuum soldering causes a reduction of the solder alloy volume and consequently further decreases the standoff height.     

Electromigration on void formation of Sn3Ag1.5Cu FCBGA solder joints

The electromigration on void formation and failure mechanism of FCBGA packages under a current density of 1 × 10⁴ A/cm² and an environmental temperature of 150 °C was investigated. Two solder/substrate combinations of Sn3Ag1.5Cu with Cu-OSP and Cu/Ni/Au were examined. A conservative failure criterion was adopted to predict the failure of package, and SEM was used to observe in situ microstructural change and failure modes.Failure was mainly attributed to void occupation along UBM/solder interfaces by the side of cathode chip of bumps with downward electron flow. The current crowding was the cause for void initiation from the entrance corner of electron flow. Two specific void locations were identified at IMC/solder and UBM/IMC interfaces, and both can co-exist in the same specimen but in different bumps. No coupling mode of void was found. Since there is a discrepancy of diffusion rate between solder and IMC layers, current density results in more voids between them. A current density of 1 × 10⁴ A/cm² was found as a dominant factor that was high enough for void pattern at IMC/solder interface. However, the void formation at the UBM/IMC interface was generally induced by the UBM consumption due to the high temperature of 150 °C that dominates the void morphology crucially at UBM/IMC interface.     

Finite element analysis of the effect of process-induced voids on the fatigue lifetime of a lead-free solder joint under thermal cycling

Process-induced voids remain one of the key concerns in thermo-mechanical reliability of solder alloys. Previous studies reported that the void effect on fatigue failure reliability of solder joints depends on the void configuration and some other specific characteristics of the electronic package. This paper investigates the void effect on the solder material layers used in power modules subjected to thermal passive cycles. The Anand's visco-plastic model of the solder alloy is identified based on experimental data obtained with a micro-tester. The constitutive model is then used in a finite element analysis to study the behaviour of Innolot Pb-free solder joint used in an electronic assembly. An algorithm called Monte Carlo Representative Volume Element Generator is used to generate, based on the statistical probability law for the diameters, the 2D disk distribution of the voids (thereafter extruded in the form of cylinders) within the solder layer. The dissipated plastic energy is considered as a damage variable indicator representing the void effect on the fatigue lifetime of the solder. Results suggest that the fatigue reliability of solder joints depends not only on the size, location and ratio of the voids but also on their statistical distribution. The critical sites for damage are located at the corners of the joint, as well as at the border of voids. Fatigue lifetime of the solder joint decreases as the volume fraction of voids increases. Moreover, voids near the critical sites facilitate initiation of damage significantly. On the contrary, the solder joint behaviour is almost not affected by voids located far from the critical sites.     

热循环加载片式元器件带空洞无铅焊点的可靠性

建立了片式元器件带空洞无铅焊点有限元分析模型,研究了热循环加载条件下空洞位置和空洞面积对焊点热疲劳寿命的影响.结果表明:热循环加载条件下空洞位置和空洞面积显著影响焊点热疲劳寿命.空洞位置固定于焊点中部且面积分别为7.065×10-4,1.256×10-3,1.963×10-3和2.826×10-3mm2时,焊点热疲劳寿...     

Failure analysis of solder bumped flip chip on low-cost substrates

Failure analyses of 63/37 Sn/Pb solder bumped flip chip assemblies with underfill encapsulant are presented in this study, Emphasis is placed on solder flowed-out, nonuniform underfill and voids, and delaminations. The X-ray, scanning acoustic microscope (SAM), and tomographic acoustic micro imaging (TAMI) techniques are used to analyze the failed samples. Also, cross sections are examined for a better understanding of the failure mechanisms. Furthermore, temperature dependent nonlinear finite element analyses together with fracture mechanics are used to determine the effects of underfill void sizes on the flip chip solder joint reliability     

Effect of voids on the reliability of BGA/CSP solder joints

Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of many factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on investigating the effect of voids on the reliability of solder joints. The size, location and frequency effects on the reliability were studied. Testing was done by mechanical deflection testing (torsion) system and air to air thermal cycling (−40 °C/125 °C). Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids reduce the life of the solder joint. Voids which are greater than 50% of the solder joint area, decrease the mechanical robustness of the solder joints. Small voids also have an effect on the reliability, but it is dependent on the void frequency and location.     

Shear strength of LED solder joints using SAC-nano Cu solder pastes

The addition of Cu nanoparticles into the solder pastes by mechanical mixing method creates a positive effect on the microstructure refinement of the LED solder joints. The grain size of β-Sn and Cu₆Sn₅ decrease obviously due to the increasing concentration of the nanoparticles in the solder pastes. However, the addition of nanoparticles facilitates the formation of voids in the solder joints, especially when the concentration of nanoparticles is higher than 0.5 wt% in the solder pastes. Both the microstructure refinement and void percentage affect the shear strength of the solder joints. Since the increase of the void percentage is limited when the concentration of nanoparticles increases from 0 to 0.5 wt%, the microstructure refinement shows a dominant effect on the shear performance and thus improves the shear strength of the solder joints from 49.8 to 55 MPa. Further addition of nanoparticles in the solder pastes leads to a sharp increase of the void percentage. Consequently, the shear strength of the solder joints decreases from 55 to 48.8 MPa when the concentration of doped particles increases from 0.5 to 1 wt% in the solder pastes.     

Effect of Migration and Condensation of Pre-existing Voids on Increase in Bump Resistance of Flip Chips on Flexible Substrates during Electromigration

In Pb-free solder joints formed by reflowing a bump of solder paste, voids are formed within the solder due to the residue of flux in the reflow process. These voids migrate toward the cathode contact during electromigration under current stressing. Accompanying the electromigration, resistance jumps of a few 100 mΩ were observed. It was postulated that a jump occurs when a void touches the cathode contact. This study investigated the effect of the void migration and condensation on the change in bump resistance using three-dimensional (3D) simulations and finite element analysis. It was found that there was negligible change in bump resistance during void migration towards the high-current-density region before touching the cathode contact opening. When a small void condensed on the contact opening and depleted 18.4% of the area, the bump resistance increased only 0.4 mΩ. Even when a large void depleted 81.6% of the opening, the increase in bump resistance was 3.3 mΩ. These values are approximately two orders of magnitude smaller than those reported in the literature for the change in resistance due to void migration in flip chips on flexible substrates. We conclude that the reported change in resistance was most likely that of the Al or Cu interconnection in the flip-chip samples.     

微尺寸SnAg凸点的制备技术及其互连可靠性

用电镀法制备了尺寸小于100μm的面阵列Sn-3.0Ag凸点.芯片内凸点的高度一致性约1.42%,Φ100mm硅圆片内的高度一致性约3.57%,Ag元素在凸点中分布均匀.研究了不同回流次数下SnAg/Cu的界面反应和孔洞形成机理,及其对凸点连接可靠性的影响.回流过程中SnAg与Cu之间Cu6Sn5相的生长与奥氏熟化过程相似.SnAg/Cu6Sn5界面中孔洞形成的主要原因是相转变过程中发生的体积缩减.凸点的剪切强度随着回流次数的增多而增大,且多次回流后SnAg/Cu界面仍然结合牢固.Cu6Sn5/Cu平直界面中形成的孔洞对凸点的长期可靠性构成威胁.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Mechanisms and solutions to the brittle solder joint in electroless Ni plating

Brittle solder joints in Electroless Ni electroless Pd immersion Au (ENEPIG) surface finishes are one of the key reliability issues in electronics assembly. Previous characterization of the reflow process has indicated that interfacial voids formed after solder reflow are responsible for the decreases in solder joint strength. However, the mechanisms behind the formation of these voids in the ENEPIG process remain unclear. In this paper, the interaction between various aspects of the ENEPIG process and solder joint strength were investigated. Surface roughness, morphology, and nano-pitting at the interface between electroless Pd and Ni-P were characterized. The size and density of nano voids inside Ni₂SnP were measured after the specimens were reflowed with Sn4Ag0·5Cu solder ball. Additionally, high speed shear solder joint strength measurements were made. The results indicated that anion adhesion induced nano-pitting at the interface between the Ni₂SnP intermetallic and Pd, resulting in the formation of a nano void layer during reflow. These interfacial voids lead to lower solder joint strength. Based on the results, a solution to prevent the brittle solder joint failures is suggested.