Soft breakdown in irradiated high-κ nanolaminates

In this paper the electrical characteristics of different atomic layer deposited (ALD) high permittivity dielectric films (Al₂O₃ and Al₂O₃/HfO₂ nanolaminates) subjected to ion irradiation (25 MeV oxygen ions and 10 MeV protons) are evaluated. The capacitance-voltage (C-V) and current-voltage (I-V) characterization show that high-κ nanolaminates are more tolerant to radiation than the Al₂O₃ layers, but suffer radiation soft breakdown (RSBD) events. The main variation on the electrical characterization could be interpreted as a gradual decrease of the dielectric constant and/or as an increase of the series resistance of the device.     

Stability of Si impurity in high-κ oxides

The interface structure of a high permittivity (high-κ) oxide with Si substrate affects the electrical properties of the high-κ based transistors. Our theoretical analysis suggests that the formation of a SiO₂ layer at the high-κ/Si interface originates from the instability of a Si impurity in the high-κ oxide. Our computational results revealed that the Si impurity is much more stable in La₂O₃ than in HfO₂, indicating La₂O₃ is a silicate former, while SiO₂ is likely to precipitate at the HfO₂/Si interface.     

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-κ materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-κ/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing “design for reliability” (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-κ materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-κ gate materials such as cerium oxide (CeO₂) will also be demonstrated to further illustrate the concept of DFR.     

Anomalous drain voltage dependence in bias temperature instability measurements on high-κ field effect transistors

We find that changes in threshold voltage induced by negative bias temperature stressing of p-channel field effect transistors with HfSiON gate dielectrics are modulated by the drain voltage, in measurements wherein the drain current is measured during stressing. This effect is not observed in SiO₂ gate devices. Short channel effects are excluded as explanations, leading us to conclude that positive charge in the dielectric stack is laterally mobile and is conducted out of the insulator via the drain. Further, a simple qualitative model of charging kinetics allows us to extract the density of interface states as a function of time, and shows that these defects build in time, reaching numbers on the order of 10¹¹ cm⁻² after hundreds of seconds.     

High-κ dielectric breakdown in nanoscale logic devices – Scientific insight and technology impact

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO₂-based high-κ dielectrics replacing SiO₂ and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness ∼1–2 nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.     

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al₂O₃ has been compared with similar structure consisting of Si nanocrystals in SiO₂ to validate the concept.     

Charge transport in high-κ stacks for charge-trapping memory applications: A modeling perspective (invited)

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining their similarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-κ stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-κ tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.     

Evaluation of the N- and La-induced defects in the high-κ gate stack using low frequency noise characterization

Low frequency noise (LFN) characterization was performed on the HfSiON gate stacks fabricated with the SiON interfacial layers (ILs) and a La cap layer. The LFN data identified N and La related defects located in the IL/HK region.     

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Bias Temperature Instability (BTI) is a major reliability concern in CMOS technology, especially with High-dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time-independent process-induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in BTI degradation. Since time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time-zero variability on all of these effects simultaneously. Accordingly, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~ 1000 nm²) in 30 nm technology, we observe significant effects of Random Dopant Fluctuation (RDF) on BTI-induced variability (σ_ΔVth). In addition, circuit analysis reveals similar trend in performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on V_th degradation cannot be disregarded in scaled technology and needs to be considered in variation-tolerant circuit design.     

Time dependent breakdown characteristics of parylene dielectric in metal–insulator–metal capacitors

In this work, we present reliability results of MIM (Metal–Insulator–Metal) capacitors fabricated with parylene as the dielectric, deposited at room temperature. We have evaluated the time dependent dielectric breakdown (TDDB) of parylene-based MIM capacitors as a function of constant DC voltage stress, area and dielectric thickness of the capacitor. Mean-time-to-failure (MTTF) of parylene evaluated at different stress voltages shows a power law distribution over the applied voltage range and device area, with MTTF driven by the number of defects. Defect density in the parylene capacitors is also reported and is calculated to be ～1.2 × 10³ defects/cm².     

Investigating the impact of the defect dynamic characteristics on the PBTI in the high-κ gate device

Recent device reliability studies on the metal/high-κ device observed the inter-convertible characteristics of the electron trap levels between the shallow and deep defect states under cyclic positive-bias temperature stressing. Although the oxygen vacancy and oxygen interstitial defect, being two typical types of defects in the high-κ oxide, have been criticized as the culprit for the device reliability issue and investigated in many simulations, all results have indicated that the defect levels induced by them were either too shallow or too deep and failed to explain the above experimental observation. Nevertheless, studies on the static characteristics of vacancy-interstitial (V_O-O_i) model showed scattering distributed electron trap levels within the bandgap, making it as a promising defect type that can account for the above experimental observation. In this work, we investigated the dynamic characteristics of the V_O-O_i defect pair under PBTI stress by tuning the relative position of V_O and O_i. Our simulation results show multiple energy barriers for the structure transformation along the O_i migration path, and the charge trap level of the specific defect pair during the O_i migration is shown to be adjustable within the HfO₂ band gap, depending on the O_i positions. These results depict an atomic picture to help us understand the defect electrical behavior under cyclic positive bias stress condition.     

Stack engineering of TANOS charge-trap flash memory cell using high-κ ZrO2 grown by ALD as charge trapping layer

ZrO₂ with a κ value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si₃N₄ in TANOS-like memory capacitors, with Al₂O₃ as blocking oxide, SiO₂ as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO₂ exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si₃N₄ based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 °C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO₂ down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO₂ in next generation charge trapping nonvolatile memories.     

Interplay of plasma etch, strip and wet clean in patterning La2O3/HfO2-containing high-κ/metal gate stacks

The removal process of the La₂O₃/HfO₂ dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch-clean process. Both processes meet the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut.     

On the nature of electroluminescence at 1.5 μm in the breakdown mode of reverse-biased Er-doped silicon <Emphasis Type="Italic">p-n</Emphasis>-junction structures grown by sublimation molecular beam epitaxy

Electroluminescence features in the wavelength range of 0.9–1.65 μm were experimentally studied in the breakdown mode of reverse biased Si/Si:Er/Si p-n-junction structures grown by sublimation molecular-beam epitaxy. Based on the results of this study, a new physical model is proposed, in which radiative transitions in the near-infrared region are excited by recombination of electrons arriving at corresponding energy levels in the Si:Er layer due to their tunneling from the valence band of the p ⁺-layer in the electric field of the reverse biased p-n-junction. The model proposed is in qualitative agreement with main available experimental results.     

A compare of electrical characteristics in Al/p-Si (MS) and Al/C20H12/p-Si (MPS) type diodes using current–voltage (I–V) and capacitance–voltage (C–V) measurements

In this study, both the metal-semiconductor (MS) and metal-polymer-semiconductor (MPS), (Al/C₂₀H₁₂/p-Si), type Schottky barrier diodes (SBDs) were fabricated using spin coating method and they were called as D₁ and D₂ diodes, respectively. Their electrical characterization have been investigated and compared using the forward and reverse bias I–V and C–V measurements at room temperature. The main electrical parameters such as ideality factor (n), reverse saturation current (I_o), zero-bias barrier height (Φ_Bo), series (R_s) and shunt (R_sh) resistances, energy dependent profile of interface states (N_ss), the doping concentration of acceptor atoms (N_A) and depletion layer width (W_D) were determined and compared each other and literature. The rectifying ratio (RR) and leakage current (I_R) at ±3 V were found as 2.06×10³, 1.61×10⁻⁶ A and 15.7×10³, 2.75×10⁻⁷ A for D₁ and D₂, respectively. Similarly, the R_s and R_sh values of these diodes were found as 544 Ω, 10.7 MΩ and 716 Ω and 1.83 MΩ using Ohm’s Law, respectively. In addition, energy and voltage dependent profiles of N_ss were obtained using the forward bias I–V data by taking into account voltage dependent effective barrier height (Φ_e) and n and low-high frequency capacitance (C_LF–C_HF) methods, respectively. The obtained value of N_ss for D₂ (MPS) diode at about the mid-gap of Si is about two times lower than D₁ (MS) type diode. Experimental results confirmed that the performance in MPS type SBD is considerably high according to MS diode in the respect of lower values of N_ss, R_s and I_o and higher values of RR and R_sh.