10Gb/s0.25m CMOS1∶4键合分接器

首先分析了1∶4分接器的树型结构及其主要特点。在此基础上,进一步探讨了树型结构中所用的1∶2分接器,并给出其中的锁存器电路结构。此外,还讨论了分频器电路及输入输出电路。最后分析了超高速键合电路并给出测试方案。测试结果表明,在采用标准0.25μmCMOS工艺设计的分接器中,本设计首次达到键合后能够在STM-16和STM-64所要求的数据速率上稳定工作的性能,最高工作速率达10.58Gb/s。     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

Study of a SiGe-HBT-based 1：2 demultiplexer IC up to 100 Gb/s rate

An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis sho...     

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology

A fully integrated OC-768 clock and data recovery IC with SFI-5 1:16 demultiplexer is designed in a 120-GHz/100-GHz (f/sub T//f/sub MAX/) SiGe technology. The 16 2.5-Gb/s outputs and additional deskew channel are compliant with the Serdes Framer Implementation Agreement Level 5 specification. The measured bit-error rate is <10/sup -15/. The measured jitter tolerance exceeds the mask specified in G.8251. The IC operates with 1.8-V and -5.2-V supplies and dissipates 7.5 W.     

A fully integrated 40-Gb/s clock and data recovery IC with 1:4DEMUX in SiGe technology

In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors' best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10^-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10^-10 requires an optical signal-to-noise ratio of 23.3 dB     

Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors

Using InP-InGaAs heterojunction bipolar transistor (HBT) technology, we have successfully designed and fabricated a low-power 1:16 demultiplexer (DEMUX) integrated circuit (IC) and one-chip clock and data recovery (CDR) with a 1:4 DEMUX IC for 10-Gb/s optical communications systems. The InP-InGaAs HBTs were fabricated by a nonself-aligned process for high uniformity of device characteristics and producibility. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consist of approximately 1200 and 460 transistors, respectively. We have confirmed error-free operation at 10 Gb/s for all data outputs of both ICs. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consume only 1 W and 950 mW, respectively. These results demonstrate the feasibility of InP-InGaAs HBTs for low power high-integration optical communication ICs.     

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture

An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of -4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.     

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optictransmission

We report a new integrated circuit for multiplexing and demultiplexing at rates of 100 Gb/s. In transistor multiplexer/demultiplexer circuits, the operating data rate is limited by transistor bandwidth. The demonstrated circuit, which uses terahertz Schottky diodes, readily attains the necessary bandwidths. The IC, based in the diode nonlinear-transmission line (NLTL) technology, consists of an array of four sample-hold gates driven by NLTL strobe generators. To permit use in multiplexing, the sample-hold gates use a six-diode configuration with 150 GHz output bandwidth. Initial measurements with simple data patterns at 104 Gb/s are demonstrated     

单片集成光波导波分器的研究

简述了单片集成光波导波分器的原理和制备工艺。并用同一根光纤传输的两波长激光束（６３２．８ｕｍ，７８５．５ｕｍ）测试了该器件的波分特性。实验中成功地观察到同光纤传输的两个不同波长的激光信号在波分器的输出端分离。     

A 0.18-/spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.     

Silicon bipolar integrated circuits for multi-Gb/second opticalcommunication systems

The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs and hybrid circuit modules operate at multi-Gb/s data rates. The performance of these ICs indicates that advanced silicon bipolar integrated circuits with their high speed, functionality and low cost potential could play an important role in alleviating the electronic bottleneck in future multigigabit optical communication systems     

Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.      

Monolithic integrated 4:1 multiplexer and demultiplexer operating up to 4.8 Gbit/s

The letter describes the high-speed performance of a 4:1 time-division MSI multiplexer and demultiplexer, which are fabricated using advanced super self-aligned process technology (SST). The maximum operation speed of the multiplexer is 5.02 GHz under 576 mW power dissipation. The system, which is composed of a multiplexer and a demultiplexer, operates at up to 4.80 GHz. The demultiplexer has a power dissipation of 1148 mW. Interchannel interference is also examined.     

A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS

A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875 × 640 μm2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.     

WDM access system based on shared demultiplexer and MMF links

A wavelength-division-multiplexing (WDM) access system can be used in two basic ways: user multiplexing, which assigns a wavelength to each user, and service multiplexing, which assigns a wavelength to each service. In current designs for service multiplexing, each optical network unit (ONU) must have a demultiplexer that can select any wavelength. This paper proposes a new WDM access system that uses one demultiplexer shared by many ONUs to offer optical-distribution access services. This system realizes significant cost reductions due to its passive optical network (PON) architecture, high capacity due to its WDM technology, and easy wiring through the use of multimode fiber (MMF). As one of the realization approaches of the shared demultiplexer, we explain the principle and configuration of a shared demultiplexer based on diffraction theory, and present theoretical and experimental analyses of a prototype 4/spl times/(4/spl times/4) shared demultiplexer whose configuration is based on Littrow mounting. Experimental transmission performances demonstrate the feasibility of the proposed WDM access system.     

A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using asuper self-aligned selectively grown SiGe base (SSSB) bipolar transistor

This paper reports a 2.4 Gb/s optical terminal IC that integrates high-speed analog and digital circuits for future optical networks using 60-GHz f_T self-aligned silicon-germanium (SiGe)-alloy base bipolar transistors. The selective epitaxial growth (SEG) SiGe base was formed by using cold-wall ultra-high vacuum (UHV)/CVD technology. Boron concentration reduction at the SiGe epitaxial layer/Si-substrate interface by using a new treatment prior to SEG leads to electrical characteristics with less dependence on bias voltage. The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-locked loop (PLL), and a D-type flip-flop (D-F/F)), and a 1:16 demultiplexer (DMUX). An input offset control circuit is included in the AGC amplifier for wide dynamic range. Trench isolation and silicon-on-insulator (SOI) technologies are introduced to reduce crosstalk between the amplifiers and the PLL. Power consumptions are 0.6 W at -5.2 V for the analog part and 0.45 W at -3.3 V for the digital part, which does not include the ECL output buffers