A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

Design of CMOS VHF/RF Biquadratic Filters

In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G _m-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

A Low-Voltage Fully Differential MOSFET-C Bandpass-Based Voltage-Controlled Oscillator for Frequency Tuning

A low-voltage fully differential MOSEFT-C bandpass-based voltage-controlled oscillator for the purpose of frequency-tuning of filters is proposed. This oscillator is guaranteed to start oscillating and provide well-controlled amplitude. Experimental filters and the filter tuning circuit are designed to demonstrate its use. The performance of this circuit is shown by experimental results.     

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

New topology for a variable differential delay line using the FGMOS transistor

In this study, we show that floating gate MOS (metal oxide semiconductor) transistors support a low-voltage and low-power variable analogue differential delay line circuit for signals in the audio frequency range. The delay time is dependent and accomplished by a variable bias voltage. Attention is focussed on the fact that the topology will be implemented taking into account low-voltage and low-power. The CMOS (complementary metal oxide semiconductor) circuit design is based on the G _m ? C low-pass linear integrator as the main core. This way, a delay line circuit with two taps was implemented in a 1.2-μm CMOS technology. The experimental results show a spurious free dynamic range of 56 dB, a total harmonic distortion of 0.56% and power dissipation of 52 μW with a supply voltage of 1.5 V.     

Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the g _m -I _D characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-m CMOS test-chip are given.     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

New electronically tunable current-mode universal biquad filter using translinear current conveyors

In this study, a new electronically tunable current-mode universal filter with two inputs and two outputs employing one translinear current conveyor, one translinear current conveyor with controlled current gain and two grounded capacitors is presented. The proposed circuit offers the following attractive features: realisation of low-pass, band-pass, high-pass, band-stop and all-pass current responses from the same configuration; employment of the minimum active and passive components; no requirement of component matching conditions; independent current-control of the parameters natural frequency (ω_o) and quality factor (Q); low active and passive sensitivities; and high impedance output. The characteristics of the proposed circuit are simulated using PSPICE to confirm the theory.     

一种自适应时间常数匹配Gm-C电感电流采样方法

提出了一种自适应时间常数匹配G_m-C电感电流采样方法。该方法通过比较Buck变换器SW点电压的过零时间与G_m-C滤波采样电压的过零时间,判断G_m-C时间常数是否与DCR时间常数匹配。使用鉴频鉴相器检测二者过零时间差,并控制双向计数器,实现对电容阵列等效容值的调制,最终实现自适应时间常数匹配G_m-C电感电流采样。与前序工作相比,该校准过程平滑,并且可以在DC-DC变换器正常工作情况下进行在线调制,能有效适应DC-DC变换器工作中温度、电压、电流等外部条件的变化。     

Delay-Range-Dependent L 2–L ∞ Filtering for Stochastic Systems with Time-Varying Interval Delay

This paper focuses on the problem of delay-range-dependent L ₂–L _∞ filter design for stochastic systems with time-varying delay. The time delay varies in an interval. A delay-range-dependent sufficient condition is formulated in terms of linear matrix inequalities (LMIs), which guarantees the existence of a linear filter. The proposed filter ensures that the filtering error system is stochastically asymptotically stable and that its L ₂–L _∞ performance satisfies a prescribed level. The corresponding filter design is cast into a convex optimization problem which can be efficiently handled by using standard numerical algorithms. Finally, a numerical example is given to illustrate the effectiveness of the proposed method. This work is partially supported by the Natural Science Foundation of China (60674055, 60774047), and the Taishan Scholar Programme of Shandong Province.     

一款采用跨导增强技术的新型宽带低噪声放大器

A new broadband low-noise amplifier （LNA） is proposed. The conventional common gate （CG） LNA exhibits a relatively high noise figure, so active gin-boosting technology is utilized to restrain the noise generated by the input transistors and reduce the noise figure. Theory, simulation and measurement are shown. An implemented prototype using 0.13 μm CMOS technology is evaluated using on-wafer probing. S11 and S22 are below -10 dB across 0.1-5 GHz. Measurements also show a gain of 18.3 dB with a 3 dB bandwidth from 100 MHz to 2.1 GHz and an ⅡP3 of-7 dBm at 2 GHz. The measured noise figure is better than 2.5 dB below 2.1 GHz, is better than 4.5 dB below 5 GHz, and at 500 MHz, it gets its minimum value 1.8 dB. The LNA consumes 9 mA from 1.5 V supply and occupies an area of 0.04 mm^2.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

A CMOS Quadrature Baseband Frequency Synthesizer/Modulator

A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 m CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4–2.4835 GHz ISM frequency band. This frequency synthesizer/modulator is a capable of frequency and phase modulation. The major components are: a quadrature direct digital synthesizer, digital-to-analog converters and lowpass filters. By programming the quadrature direct digital synthesizer, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The quadrature baseband direct digital synthesizer produces an 80 MHz frequency band. The quadrature baseband spectrum could be upconverted with off-chip mixers into the 2.4 GHz ISM frequency band. The chip has a complexity of 17,803 transistors with a die area of 24 mm² and a core area of 9 mm². The power dissipation is 496 mW at 3.3 V.     

Preparation and Thermoelectric Properties of Ag<Subscript>0.5</Subscript>In<Subscript>0.5−<Emphasis Type="Italic">x</Emphasis></Subscript>Pb<Subscript>5</Subscript>Sn<Subscript>4</Subscript>Te<Subscript>10</Subscript>

A series of compounds with composition Ag_0.5In_0.5−x Pb₅Sn₄Te₁₀ (x = 0.05 to 0.20) were prepared by slowly cooling the melts of the corresponding elements, and the effect of In content on the thermoelectric transport properties of these compounds has been investigated. Results indicate that the compounds’ electronic structure is sensitive to In content, and that the carrier concentration of these compounds at room temperature increases from 4.86 × 10¹⁸ cm⁻³ to 3.85 × 10²¹ cm⁻³ as x increases from 0.05 to 0.20. For these compounds, electrical conductivity decreases and Seebeck coefficient increases with increasing In content. Ag_0.05In_0.03Pb_0.5Sn_0.4Te₁₀ shows very low lattice thermal conductivity, and has a maximum dimensionless figure of merit ZT of 1.2 at 800 K.     

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing

The effectiveness of single threshold I _DDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta I _DDQ is identified as one alternative for deep submicron current measurements. Often delta I _DDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the I _DDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate I _DDQ limits for normal and stressed operating conditions of 0.18 m n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed I _DDQ testing is also investigated.     

An Analog Self-Test Based on Differential I DD Monitoring Supported by Differential I OUT Checking

This paper proposes a novel DFT scheme that combines two test techniques—differential power supply current (I _DD ) monitoring and differential output current (I _OUT ) checking—in a single analog self-test. The DFT scheme is aimed at fully differential analog circuits. Fault detection is provided by means of differential measurement of the on-chip parameters, such as the I _DD and I _OUT currents. Due to the differential nature of the test principle used, no reference measurement is required prior to the test, thus the fault detection exhibits a significantly reduced dependency on process parameter variations, variation of temperature during the test as well as outside interference's. Based on measurement results, the realistic tolerance band for fault detection was determined and the fault coverage, resulting from previous simulation experiments, was adjusted.     

S/N Optimized, Programmable 1–10 MHz Bandwidth and 0–20 dB Gain, Precision I-Q Communication Channel for Digital Video Applications

An analog part of a digital-video quadrature demodulation scheme is built using a 7 GHz, 0.8 m biCMOS process. The scheme provides for 1–10 MHz cutoff frequency and 0–20 dB gain controls and dissipates 250 mW from a power supply of 5 V. The channel filtering is realized by two identical 4th Order Butterworth lowpass filters built with the g _m -C technique. They are equipped with cutoff programming and in-package trim tuning for cutoff adjustment. A programmable gain amplifier is placed in front of each filter for better joint noise and intermodulation performance. Such an arrangement allows to operate the filter at a maximum signal level improving the worst-case channel S/N by 6.5 dB. For the in-band components the worst case S/N is better than 41 dB, whereas THD and IMD are less than –48 dB. This single-ended channel achieves PSRR of 42 dB.