Validation of yield models with CMOS/SOS test structures

A methodology assessed to implement wafer level reliability relies on the design of specific test structures which must be as similar as possible to functional circuits geometries and lay-outs. In a second step, electrical tests provide wafer level data to validate the use of the Poisson yield model which gives defect densities. It is found that chips from the central area of the wafer present randomly distributed defects whereas those from the periphery are governed by a more systematic distribution.     

A hierarchical defect repair approach for hybrid nano/CMOS memory reliability enhancement

Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misalignments, line width variations and contamination particles. In this paper, initially a method is proposed for separately identifying cluster defects from random ones. Subsequently a hardware repair structure is presented to repair the cluster defects with rectangular window transfer vectors using a range-matching content addressable memory (RM-CAM) and random defects using defect aware triple-modular redundancy (DA-TMR) columns. It is shown that a combination of these two approaches is more effective for repairing defects at higher error rates with an acceptable overhead. The effectiveness of the technique is shown by examining defect recovery results for different fault distribution scenarios. Also the mapping circuit hardware performance parameters are presented for various memory sizes and the speed, power dissipation and overhead factors are reported.     

Optimized redundancy selection based on failure-related yield modelfor 64-Mb DRAM and beyond

An optimized redundancy scheme for 64-Mb dynamic RAM (DRAM) and beyond that is based on a failure-related yield model is described. This model accounts for three-dimensional memory cell structures and individual design rules used in individual sections of the chip. Failure-mode parameters for the model are determined by performing a trial fuse-blowing test on 4-Mb DRAMs. The test employs a memory tester without requiring complicated visual inspections. The dependence of the yield on block division and the number of spare elements for a 64-Mb DRAM are investigated. In the estimation as a redundancy scheme for the 64-Mb DRAM, more than two spare rows and two spare columns in 1-Mb or less subblocks are shown to be necessary     

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.      

基于像素分布特性的IC晶片视觉检测方法

IC晶片制造过程存在多种致命缺陷,致使芯片失效,导致成品率下降.冗余物缺陷是影响IC晶片成品率下降的重要原因,主要造成电路短路错误.针对冗余物缺陷对版图的影响,提出了一种简单可行的缺陷视觉检测方法,以实现冗余物缺陷的识别及电路失效形式的确定.根据摄取的显微图像的图像特征,利用光线补偿技术及形态滤波方法消除干扰噪声,以提高图像质量,采用投影定理及基于像素分布特性的检测方法,实现电路短路形式或缺陷未导致电路失效的识别.     

Memory Defect Tolerance Architectures for Nanotechnologies

Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing in future submicron technologies, more advanced solutions may be required for memories to be produced in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels of several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents several Built-In Self Repair techniques addressing memories affected by high defect densities as well as an evaluation of the area cost and yield. Statistical fault injection simulations were conducted and the obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.     

Redundancy in LSI memory array

The probability of array yield for a large-scale integrated memory array is considered. The calculation assumes the random distribution of defective cells and the discretionary wiring of good rows and columns. Under the above conditions, the calculation shows that the most efficient use of redundancy is to have more row or column redundancy along the longer dimension of the array.     

相邻层冗余共享的三维存储器成品率优化方法

存储裸片堆叠方案和冗余共享策略对提高三维存储器成品率有重要影响.为提高三维存储器的成品率并且减少行列冗余所需的TSVs数量,提出了一种相邻层冗余共享结构.该冗余共享结构使得每层存储裸片的行列冗余不仅能被本层使用,而且能被相邻层使用.并在此结构的基础上,提出了一种新的存储裸片堆叠方案.该方案通过构建存储裸片的选择限制条件,每次选中适合的存储裸片来堆叠三维存储器以充分利用行列冗余.实验结果表明,与国际上同类方法相比,所提方案有效地提高了三维存储器的成品率,并且减少了行列冗余所需的TSVs数量.     

Defect clustering viewed through generalized Poisson distribution

It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported     

A simulation-based semiconductor chip yield model incorporating a new defect cluster index

This paper proposes a new cluster index that utilizes the defect location data on a wafer in terms of the coefficient of variation. The proposed cluster index is independent of the chip area and does not require assumptions on the distribution of defects. An extensive simulation is performed under a variety of cluster patterns and a yield prediction model is derived through the regression analysis to relate the yield with the proposed cluster index and the average number of defects per chip. The performance of the proposed simulation-based yield prediction model is compared with that of the well-known negative binomial model.     

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85?%, a relative yield improvement of 118.79?% is obtained with two redundant layers, while this is 14.03?% only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68?% when using layer redundancy and only with 12.48?% when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.     

Ultra large scale static rams

Using a patented defect avoidance technique, high yield production of high density SRAM devices (ULSI SRAMs) can be achieved one process generation ahead of the rest of the industry. Production wafer yields as high as 100% and long-term average yields above 80% are reported on Inova's monolithic, 1.2μ, 320 square mm, one megabit SRAM demonstrating a practical method of achieving wafer scale integration. A yield model is presented and used to determine the optimized architecture and redundancy scheme for Inova's four megabit SRAM and to predict yield as a function of defect density. Achievement of a working 8M-bit experimental device using a 1.2μ process is also reported.     

Yield optimization in large RAM's with hierarchical redundancy

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala et al., 1988) is considered as an example for modeling and optimization. The results show that the two-level hierarchical redundancy approach, with spare bit and word lines within memory quadrants, and additional spare modules for global sparing, along with redundant interconnections can efficiently provide defect tolerance and viable yields for future generations of high-density dynamic random access memories     

A novel associative approach for fault-tolerant MOS RAMs

A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well.     

A discussion of yield modeling with defect clustering, circuitrepair, and circuit redundancy

The mathematical foundation of common integrated--circuit yield models based on the assumption that the yield is dominated by random point defects is discussed. Various mathematical models which are commonly used to account for defect clustering are given a physical interpretation and are compared mathematically and graphically. A yield model applicable when the repair of some defects in a chip is possible is developed and discussed. Simple yield models for systems with two-fold block redundancy and triple modular redundancy in the presence of defect clustering are developed. and the implications for overall system yield are discussed. It is shown that the yield of systems with circuit redundancy can be substantially affected by defect clustering and, hence, that a correct understanding of defects and yield is essential to predict the yields and costs of wafer-scale products     

Poisson process and integrated circuit yield prediction

Initial integrated circuit yield predictions were overly pessimistic because the assumption that defects were a homogeneous random population led to the logarithm of yield linearly declining with increasing chip area. In reality, the yield vs area curve is concave up, which can be successfully modeled by partitioning the wafer into several Poisson subareas of different defect densities. Previously, this partitioning was done by “eye”. Here an algorithm has been developed to do the partitioning. Good results over a wide range of yields have been obtained. For the particular data presented, the yield curves in the range of interest can be described by a negative binomial distribution, which implies the underlying defect density is governed by the gamma distribution. As previously anticipated, both led to overpredictions of the yield for large chip areas.     

Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024/spl times/2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.     

Probabilistic crisscross error correction

The crisscross error model in data arrays is considered, where the corrupted symbols are confined to a prescribed number of rows or columns (or both). Under the additional assumption that the corrupted entries are uniformly distributed over the channel alphabet, and by allowing a small decoding error probability, a coding scheme is presented where the redundancy can get close to one half the redundancy required in minimum-distance decoding of crisscross errors     

Defect cluster analysis for wafer-scale integration

A methodology for characterizing spatial defect distributions is presented. A correlation function approach providing spatial information not measurable with classical methods such as yield-versus-area curves is described. This additional information includes the spatial extent of defect clustering, the strength of clustering, and uncertainty in clustering magnitude. The correlation function methods are applicable to experimentally determined defect maps or to simulation results based on different assumptions concerning the spatial distribution of defects. It is also shown that the approach is useful in predicting yield for redundant circuit configurations when experimental data pertaining to the spatial distribution of defects are available. This type of yield prediction capability is important for judging the feasibility of various redundancy implementations, including wafer scale integration     

Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy

In the optimization of the number of good chips per wafer, yield is obviously one key factor. It plays the major role in the manufacturing phase, as at this time circuit design and chip area cannot be modified. In the design phase, however, chip area as the second factor defining good chips per wafer can still be influenced. If there are no strong relationships between yield and chip area, both can be optimized independently. In some cases, however, there are such strong relationships, and an optimum of yield gain versus area growth has to be found. Maybe the most important example where strong relationships between area and yield have to be considered is the estimation of optimum memory redundancy. In this paper, we will review and discuss relationships between yield and area and present methods for optimization of good chips per wafer, with special focus on the optimization of memory redundancy