Switched-current memory circuits for high-precision applications

We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-μm CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz     

A Direct PWM Technique for a Single-Phase Full-Bridge Inverter Through Controlled Capacitor Charging

The controlled-capacitor-charging (CCC) technique is utilized in this paper to synthesize a sinusoidal voltage at the output from the unregulated dc at the input. The method is based on the controlled charging/discharging of a capacitor to realize the desired voltage waveform. A capacitor that is connected across the load is charged/discharged through an inductor by applying high-frequency pulses. The applied pulses could be of either positive or negative polarity, depending on the error signal in the controller. The controller senses the output voltage and current and operates to maintain zero-current switching at every turn-on while keeping the output voltage close to the reference waveform by a tracking-control algorithm, enforcing limits in maximum switching frequency and voltage ripples. This paper presents a direct method of implementing the pulsewidth modulation for the single-phase full-bridge inverter, using the CCC technique. A simple procedure to design such an inverter is also discussed. The proposed controller is simulated in a personal computer simulation program with integrated circuit emphasis. Supporting results from an experimental prototype confirm the usefulness of the proposed controller. The inverter may be used in uninterruptible power supply and many other applications.      

一种新型高性能开关电流存储单元的设计

利用一种新技术,在低压(1.8 V)条件下,设计了一种高性能的开关电流(SI)存储单元电路.该电路通过在基本存储单元基础上增加一个电压反转跟随器电路(FVF),从存储晶体管的输入端直接消除时钟馈通(CFT)误差电压,从而阻止了电流误差的产生,使得输出端的CFT误差电流降为原来的6%,并通过Hspice给出了仿真结果.结果表明所设计的电路方案正确有效.     

励磁电流负反馈对双凸极电机调压性能的影响

电励磁双凸极发电机（DSEMG）具有结构简单,可靠性高,控制方便等特点,可通过调节励磁电流大小来维持输出电压恒定。传统的调压器由于仅仅引入输出电压负反馈,稳态性能往往难以满足要求。本文首先简单介绍了电励磁双凸电机的发电原理,提出在传统调压器的基础上再引入励磁电流负反馈,通过Simulink仿真和实验验证,与传统调压方式的结果相比较,来说明这种调压方式比传统的调压方式有较高的调压精度,适合于电励磁双凸极发电机（DSEMG）。     

A novel technique to achieve unity power factor and fact transientresponse in AC-to-DC converters

This paper presents a novel power factor correction technique for single-phase boost type AC-to-DC converters in continuous conduction mode. Instead of using the inductor current or switching device current, in this paper, the diode current in the boost converter is used to formulate the duty ratio of the switch in a special way which makes the input current sinusoidal and in phase with the input voltage. To improve the dynamic performance and minimize the input current harmonic components, a new double-injection compensation method is employed in the voltage feedback loop. The power factor corrector has the following advantages: (1) operation with constant switching frequency; (2) elimination of input voltage sensing, error amplifier in the current loop and multiplier in the output voltage feedback loop; (3) minimal total harmonic distortion in the input current; (4) fast dynamic response of the output voltage loop; and (5) simple implementation of the control circuit. The principles of operation of the proposed control scheme are explained. Simulation and experimental results are presented to verify the feasibility of the control strategy     

Macromodeling of nonlinear digital I/O drivers

In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital input/output (I/O) drivers. This method takes into account both the static and the dynamic memory characteristics of the driver during modeling. Spline function with finite time difference approximation includes the previous time instances of the driver output voltage/current to capture the output dynamic characteristics of digital drivers accurately. In this paper, the speed and the accuracy of the proposed method is analyzed and compared with the radial basis function (RBF) modeling technique, for modeling different test cases. For power supply noise analysis, the proposed method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and cross talk accurately when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on recurrent artificial neural networks (RNN) is discussed.     

一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了10 0倍.     

Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push–Pull Techniques for Enhancing Transient Performance

An adaptive reference control (ARC) technique is proposed for minimizing overshoot/undershoot voltage and settling time of low-dropout regulators. Linear operation provided by the ARC technique can dynamically and smoothly adjust the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In addition, a dynamic push-pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5%, and 70%, respectively, when load current changes between 1 and 100 mA.     

Design and implementation of a high precision and wide range adjustable LED drive controller

This paper presents a novel high precision and wide range adjustable LED constant-current drive controller design. Compared with the traditional technique, the conventional mirror resistance is substituted by a MOSFET with fixed drain voltage, and a negative feedback amplifier is used to keep all mirror device voltages equal, so that the output current is precise and not affected by the load supply voltage. In addition, the electric property of the mirror MOSFET is optimized by a current subsection mirror (CSM) mechanism, thus ensuring a wide range of output current with high accuracy. A three-channel LED driver chip based on this project is designed and fabricated in the TSMC 0.6 μm BCD process with a die area of 1.1 × 0.7 mm~2. Experimental results show that the proposed LED drive controller works well,and, as expected, the output current can be maintained from 5 to 60 mA. A relative current accuracy error of less than 1% and a maximal relative current matching error of 1.5% are successfully achieved.     

峰值电流模DC-DC转换器中多功能误差放大器电路设计

提出了一种适合于峰值电流模DC-DC转换器的新型多功能误差放大器电路.与斜坡电压信号结合可实现软启动功能,实现了从启动阶段到稳定工作状态的平滑过渡,无扰动出现,并有效地消除了启动阶段的浪涌电流和电压过冲;同时还具有最大电流限制和模式切换功能.该误差放大器集成到一款峰值电流模升压型DC-DC转换器中,电路采用CSMC 0.5μm BCD工艺实现.仿真结果表明：3.5V的输入电压下,误差放大器消耗的静态电流为4.48μA,并且能够实现软启动、最大电流限制、模式切换功能.电路具有简单易实现,功耗低的特点.     

一种新型Class AB开关电流存储单元的设计

设计了一种新型高性能Class AB开关电流(SI)第一代存储单元电路。电路由对称的电压反转跟随器(FVF)连接Class AB SI存储单元组成,输入级采用电流传输器结构,输出级采用可调共源共栅结构,电路具有误差小、功耗低、性能高等特点。基于此存储单元,设计了延时器和双线性积分器进行验证。电路采用SMIC 0.18μm工艺,在Spectre中进行仿真。结果表明,该存储单元具有较好的性能和应用价值。     

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage.     

Optimization of word-line booster circuits for low-voltage flashmemories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed     

An on-chip 96.5% current efficiency CMOS linear regulator using aflexible control technique of output current

This paper proposes an on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current (FCOC). By the use of the FCOC technique, the proposed circuit realizes flexible output current drive according to the load current variation. Therefore, the proposed linear regulator ran supply stable output voltage using the FCOC technique. The linear regulator is fabricated by double-metal 1.2-μm CMOS technology. The number of transistors is 46 and the die size is 0.423 mm². The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV_p-p at a frequency of output current f(I_out) ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can achieve 96.5% current efficiency     

Practical Implementation of a High-Frequency Current-Sense Technique for VRM

To track the inductor current in high-frequency dc/dc converters is not effortless, particularly when high output currents and low output voltages are demanded by the load. This paper proposes a simple technique to obtain a good accuracy in the inductor current measurement in voltage regulator module (VRM) applications. The main idea is to obtain an equivalent voltage image which can be used for the high-frequency pulsewidth modulation controller to generate the converter control law. This strategy of measurement is generic, and it has been previously validated by simulations. Afterward, some experimental results are obtained by using several prototypes of dc/dc converters delivering a very low output voltage and owning several loads from 10-mA to 100-A currents. This wide range covers the power requirements of portable and embedded VRM applications. Moreover, this sense technique has also been validated in a digital high-frequency current-mode-controlled dc/dc converter.      

Modeling of voltage output charge-pump phase frequency detector in tuning loops

Resonant inverters mostly employ tuning loops based on a phase-locked-loop (PLL) circuit. Some commercially available PLL chips, frequently used in this application, include a voltage output charge-pump phase frequency detector (CP/PFD) rather than well-known current output CP/PFD, which complicates the analysis of the loop. We present a new model for voltage output CP/PFD and an analysis of a tuning loop using this model. The proposed model employs the resistance multiplication approach, which is applicable for the circuits containing periodically operated switches. It is shown that a voltage output CP/PFD in conjunction with a simple RC low-pass filter can be modeled using a dc voltage source, a phase error controlled resistor, and a capacitor. The theoretical study is verified by experimental results.     

Very Low Power, Low Voltage, High Accuracy, and High Performance Current Mirror

A novel low power and low voltage current mirror with a very low current copy error is presented and the principle of its operation is discussed.In this circuit,the gain boosting regulated cascode scheme is used to improve the output resistance,while using inverter as an amplifier.The simulation results with HSPICE in TSMC 0.18 μm CMOS technology are given,which verify the high performance of the proposed structure.Simulation results show an input resistance of 0.014 Ω and an output resistance of 3 GΩ.The current copy error is favorable as low as 0.002％ together with an input (the minimum input voltage of vin,min～ 0.24 V) and an output (the minimum output voltage of vout,min～ 0.16 V) compliances while working with the 1 V power supply and the 50 μA input current.The current copy error is near zero at the input current of 27 μA.It consumes only 76 μW and introduces a very low output offset current of 50 pA.     

Inverter Nonlinearity Compensation in the Presence of Current Measurement Errors and Switching Device Parameter Uncertainties

This paper proposes a compensation strategy for the unwanted disturbance voltage due to inverter nonlinearity. We employ an emerging learning technique called support vector regression (SVR). SVR constructs a motor dynamic voltage model by a linear combination of the current samples in real time. The model exhibits fast observer dynamics and robustness to observation noise. Then the disturbance voltage is estimated by subtracting the constructed voltage model from the current controller output. The proposed method compensates for all of the inverter nonlinearity factors at the same time. All the processes in estimating distortions are independent of the dead time and power device parameters. From the analysis of the effect on current measurement errors, we confirmed that the sampling error had little negative impact on the proposed estimation method. Experiments demonstrate the superiority of the proposed method in suppressing voltage distortions caused by inverter nonlinearity     

一种用于非致冷红外焦平面读出电路的带隙基准源

设计了一种用于新型非致冷红外焦平面阵列读出电路的低温漂低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术.通过改进带隙基准电路中的带隙负载结构及基准核心电路,可以分别对基准电压和基准电流进行温度补偿.在0.5μm CMOS N阱工艺条件下,采用Spectre软件进行了模拟验证.仿真结果表明,在3.3 V条...     

Analysis and Design of a Novel Three-Phase AC–DC Buck-Boost Converter

This paper proposes a novel three-phase ac-dc buck-boost converter. The proposed converter uses four active switches, which are driven by only one control signal. This converter is operated in discontinuous conduction mode (DCM) by using the pulsewidth modulation (PWM) technique, and the control scheme very easily and simply achieves purely sinusoidal input current, high power factor, low total harmonic distortion of the input current and step-up/down output voltage. Also, the proposed converter provides a constant average current to the output capacitor and load in each switching period. Thus, the ripple component of sixth times line frequency will not appear in the output voltage. Therefore, a smaller output capacitor can be used in the proposed converter. Moreover, the steady-state analysis of voltage gain and boundary operating condition are presented. Also, the selections of inductor, output capacitor and input filter are depicted. Finally, a prototype circuit with simple control logic is implemented to illustrate the theoretical analysis.