Effect of GaAs/AlGaAs quantum-well structure on refractive index

We investigate the refractive index difference between the GaAs/AlGaAs quantum wells (QWs) and bulk AlGaAs. We find the refractive index difference is smaller when the electric field in the nominally intrinsic MQW region is larger, or when the well (GaAs) thickness of the QW's is larger, or when the Al fraction of the QWs is smaller. The maximum refractive index difference between the 100 Å GaAs/100 Å Al_0.2Ga_0.8As QWs at zero electric filed and bulk Al_0.1Ga_0.9As is about 0.044. Even with a small refractive index difference of 0.0132, the OFF-state reflectance of a normally-off MQW modulator at the designed photon wavelength will increase from the desired value of 0% to 90% when the reflectivity of the bottom mirror is 0.99     

Effect of parameter variations on the performance of GaAs/AlGaAsmultiple-quantum-well electroabsorption modulators

A theoretical investigation is presented of the dependence of electroabsorption in GaAs/Al_xGa_1-xAs multiple-quantum-well (MQW) structures on the MQW parameters (Al mole fraction x, well thickness L_z barrier thickness L_b and interface quality) and on the applied electric field studied. The on/off ratio of a modulator using MQWs with x=0.45, L_z=75 Å, and L _b=78 Å is predicted to increase by 20% compared to that of a modulator using MQWs with x=0.3, L_z =100 Å, and L_b=100 Å, when the MQW total active region thickness is 1 μm     

Power performance of InP-based single and double heterojunctionbipolar transistors

The microwave and power performance of fabricated InP-based single and double heterojunction bipolar transistors (HBTs) is presented. The single heterojunction bipolar transistors (SHBTs), which had a 5000 Å InGaAs collector, had BV_CEO of 7.2 V and J_Cmax of 2×10⁵ A/cm². The resulting HBTs with 2×10 μm² emitters produced up to 1.1 mW/μm2 at 8 GHz with efficiencies over 30%. Double heterojunction bipolar transistors (DHBTs) with a 3000-Å InP collector had a BV_CEO of 9 V and J_{c max} of 1.1×10⁵ A/cm², resulting in power densities up to 1.9 mW/μm² at 8 GHz and a peak efficiency of 46%. Similar DHBTs with a 6000 Å InP collector had a higher BV_CEO of 18 V, but the J _{c max} decreased to 0.4×10⁵ A/cm² due to current blocking at the base-collector junction. Although the 6000 Å InP collector provided higher f_max and gain than the 3000 Å collector, the lower J_{c max} reduced its maximum power density below that of the SHBT wafer. The impact on power performance of various device characteristics, such as knee voltage, breakdown voltage, and maximum current density, are analyzed and discussed     

Light nitrogen implant for preparing thin-gate oxides

We have implanted nitrogen (N⁺) into Si substrates before growing thin thermal oxides, and discovered that light N⁺ doses of 5×10¹³-5×10¹⁴/cm² reduced the oxidation rates by 20-30%. High-resolution TEMs and multiangle ellipsometry were used to study the oxides. The TEM reveals a highly uniform transition from the crystalline Si to the amorphous SiO ₂. With a fixed index of refraction at 1.458 for the ellipsometry, the two measurements gave identical oxide thickness between 25 and 144 Å, in contrast to the previously suggested 1.7 for oxides thinner than 100 Å. In addition, the oxidation retardation was accompanied with an improvement of the oxide uniformity across the 6-in Si wafers. We also present results of n-channel MOSFETs with coded channel lengths varying from 0.2 μm to 3 μm. The implications of these findings in terms of VLSI technologies and oxidation chemistry are discussed     

Sidewall-related narrow channel effect in mesa-isolatedfully-depleted ultra-thin SOI NMOS devices

The paper reports the sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI NMOS devices. Based on the study, contrary to bulk NMOS devices, for a channel width shrinking from 1 μm to 0.2 μm, the threshold voltage of mesa-isolated ultra-thin SOI NMOS devices with a 1000 Å thin film doped with 10¹⁷ cm^-3, decreases by 0.145 V for a front gate oxide of 100 Å and a sidewall oxide of 150 Å as a result of the sidewall edge effect     

Time-resolved photoluminescence system with subnanosecondresolution at wavelengths up to 1.65 μm

A system for measuring carrier lifetimes as short as 100 ps at luminescence wavelengths up to 1.65 μm has been developed. This uses the photoluminescence phase shift technique and is based around a guided-wave lithium niobate modulator with a high (5 GHz) bandwidth. Measurements have been performed on an MBE grown sample consisting of 25 Å thick quantum wells of Ga_0.47In_0.53As with 100 Å thick barriers of InP, and the lifetime was found to be 3 ns     

Electroabsorptive Fabry-Perot reflection modulators with asymmetricmirrors

A normally-on electroabsorptive surface-normal Fabry-Perot reflection modulator is reported with an on/off ratio of 22, insertion loss of 3.7 dB, and bandwidth of 3.4 nm for an operating voltage swing of 11 V. The asymmetric Fabry-Perot structure is made with asymmetric mirrors using a quarter-wavelength grating of 15 1/2-periods on the bottom and an air-semiconductor interface on the top. The active region is 1.4 μm thick and composed of 100Å GaAs/100 A Al_0.2Ga_0.8As multiple quantum wells. The structure provides both high-efficiency and bandwidth for surface-normal modulators     

Quantum-confined Stark effect modulators at 1.06 μm on GaAs

Electroabsorption modulation is achieved at or near a wavelength of 1.06 μm with In_xAl_yGa_1-x-yAs/In _xGa_1-xAs multiple-quantum-well (MQW) structures grown on GaAs substrates. The lattice mismatch (close to 2%) between the MQW and the substrate is accommodated by a compositional-step-graded buffer array. A dislocation density of less than 10⁷/cm² is estimated for the MQW region. For 80-to-100 Å well widths, a maximum electroabsorption coefficient of 8000 cm^-1 with an applied voltage of 15 V is obtained     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Effects of N distribution on charge trapping and TDDBcharacteristics of N2O annealed wet oxide

Wet pyrogenic oxide of different thicknesses was annealed in N₂O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 Å and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 Å, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N₂O annealed wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer t_BD was observed for N₂O annealed wet oxide of 51 Å compared to 98 Å. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N₂O ambient, the reliability of gate oxide will be improved in the ultrathin region     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Oxide thickness effect on boron diffusion in thin oxide p+ Si gate technology

Based on a network defect model for the diffusion of B in SiO₂ we propose that B diffuses via a peroxy linkage defect whose concentration in the oxide changes under different processing conditions. We show that as the gate oxide is scaled below 80 Å in thickness, additional chemical processes act to increase B diffusivity and decrease its activation energy, both as a function of the distance from the Si/SiO₂ interface. For a 15 Å oxide, the B diffusivity at 900°C would increase by a factor of 24 relative to diffusion in a 100 Å oxide     

Electroptic diffraction modulation in ZnO film on sapphire

An electrooptic Bragg diffraction modulator with high diffraction efficiency which utilizes a low-loss epitaxial ZnO optical waveguide on a sapphire substrate is discussed. An interdigital electrode with a spatial period of 20 μm and an aperture of 3 mm was fabricated directly on the film surface using a photolithographic technique. For the TE₀ mode at 6328 Å, a maximum diffraction efficiency of 98% has been obtained from DC to 100 kHz with an applied voltage of about 31 V. The unclamped electrooptic coefficient r ₃₃ is estimated to be 5.8×10^-12 m/V which is much larger than the clamped value of 2.6×10^-12 m/V in the literature     

The electron impact ionization rate and breakdown voltage inGaAs/Ga0.7Al0.3As MQW structures

The electron impact ionization rate (α) and breakdown voltage (V_BD) experimentally measured in a p⁺ -i-n⁺ diode structure with a GaAs/Ga_0.7Al _0.3As multiple quantum-well (MQW) i region are discussed. For structures with GaAs wells of 100 Å and barriers that vary from 7 to 60 Å in thickness, it is found that α is always less than α in bulk GaAs and that it decreases with increasing barrier thickness. The normalized V_BD also increases with increasing barrier thickness, confirming a decreasing ionization rate     

Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Thermal stability of MISFET with low-temp molecular-beamepitaxy-grown GaAs and Al0.3Ga0.7As gate ins

GaAs and Al_0.3Ga_0.7As epilayers grown at LT by MBE were used as insulators in the fabrication of MISFET devices. Parametric changes were used to evaluate the thermal stability of MISFET, to identify failure mechanisms and validate the reliability of these devices. The LT-Al_0.3Ga_0.7As MISFET showed superior thermal stability. The degradation in the performance of MISFET with 1000 Å thick LT-GaAs gate insulator was worse than those of the MESFET. On the other hand, MISFET with 250 Å thick LT-GaAs gate insulators exhibited stable characteristics with thermal stressing, LF (low frequency) noise studies on the TLM structures of MISFET layers exhibited 1/f noise in the LT-Al_0.3Ga_0.7As samples and 250 Å LT-GaAs samples; whereas the 1000 Å thick LT-GaAs samples exhibited 1/f^3/2 noise, which was attributed to: (i) the thermal noise generated at the interface of the insulator, and (ii) the active layer due to the outdiffused metallic arsenic. Reverse gate-drain current degradation experiments were carried out at 120°C, 160°C, 200°C, and 240°C. Transconductance frequency dispersion studies were carried out before and after thermal stress on these MISFET. The transconductance of MISFET with 1000 Å LT-GaAs gate insulators was degraded by 40% at 100 kHz after thermal stress. The rest of the samples exhibited stable characteristics. These results indicate that composition changes had occurred at the interface in thicker LT-GaAs MISFET structures. Thinner LT-layers are ideal for achieving higher transconductance and better thermal stability without sacrificing the power capability of MISFET     

InP/GaAsSb/InP double HBTs: a new alternative for InP-based DHBTs

We report on the physical operation and performance of MOCVD-grown abrupt heterojunction InP/GaAs_0.51Sb_0.49/InP double heterojunction bipolar transistors (DHBTs). In particular, the effect of the InP collector thickness on the breakdown voltage and on the current gain cutoff frequency is assessed and a f_T of 106 GHz is reported for a DHBT with a 400 Å base and a 2000 Å InP collector with a BV_CEO of 8 V. We show that InP/GaAsSb/InP DHBTs are characterized by a weak variation of f_T as a function of temperature. Finally, we also demonstrate that high maximum oscillation frequencies f_MAX>f_T can be achieved in scaled high-speed InP/GaAsSb/InP DHBTs, and provide estimates of the maximum cutoff frequencies achievable for this emergent but promising material system. Recent results on improved structures validate our performance predictions with cutoff frequencies well beyond 200 GHz     

Experimental determination of electroabsorption in GaAs/Al0.32Ga0.68As multiple quantum well structures as functionof well width

Electroabsorption in GaAs/Al_0.32Ga_0.68As multiple quantum well structures was experimentally studied for quantum well widths in the range 50-260 Å. The maximum obtainable change in absorption coefficient was found to increase monotonically with decreasing well width at the cost of increasing electric field     

Small offset-voltage In0.49Ga0.51P/GaAsdouble-barrier bipolar transistor

In_0.49Ga_0.51P/GaAs double-barrier bipolar transistors (DBBTs) grown by gas-source molecular beam epitaxy (GSMBE) have been fabricated and measured. This structure has two InGaP barrier layers (100 Å in thickness): one is inserted between the emitter-base (e-b) junction and the other between the base-collector (b-c) junction. An offset voltage of 26 mV and a differential current gain of 120 at room temperature were obtained with a heavily doped p⁺ (2×10¹⁹ cm^-3) base (500 Å in thickness). The small offset voltage was attributed to the similar structure of the e-b and b-c junctions and to the suppression of the hole injection current into the collector by the InGaP hole barrier at the b-c junction