一种基于SoC平台设计的AVS解码器软硬件分区结构

视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。该文针对AVS标准的算法和解码实现复杂程度,根据软硬件协同设计思想提出了一种结构划分合理的AVS高清视频解码器软硬件分区结构。根据AVS算法的特点该结构将宏块层以上部分的元素解析划归到软件解码中,将宏块层解码划为硬件处理。经验证,该结构设计可实现AVS高清码流解码,并在C语言编写的硬件平台仿真程序中得以实现。     

一种SoC架构的AVS硬件解码器设计方案

根据AVS音视频解码标准提出的算法设计了一种SoC架构的AVS解码芯片设计方案。该方案能够有效的减小纯硬件实现AVS硬件解码器的复杂度。采用软硬件协同设计的思想,降低解码器设计的难度,同时提高解码的灵活性。     

一种SoC架构的AVS硬件解码器设计方案

根据AVS音视频解码标准提出的算法设计了一种SoC架构的AVS解码芯片设计方案。该方案能够有效的减小纯硬件实现AVS硬件解码器的复杂度。采用软硬件协同设计的思想,降低解码器设计的难度,同时提高解码的灵活性。     

基于FPGA的AVS视频解码芯片验证平台设计

针对AVS视频解码芯片仿真和验证的要求,提出了基于FPGA的验证平台框架。该验证平台主要用于对AVS解码芯片进行硬件模块的验证,从而为整个视频解码芯片的开发提供可靠的依据。该平台基于Nios II软核处理器,可使软件模块和硬件模块在一个平台下真正实现软硬件协同工作。基于该平台实现了多个硬件模块和AVS视频解码芯片的验证,其结果证明了该验证平台的正确性和可靠性。     

基于AVS的软硬件协同可变长码解码器设计

提出一种基于软硬件协同方法的AVS可变长码解码器结构设计.定长码、指数哥伦布码及AVS视频标准特有的基于内容自适应二维可变长码(CA-2D-VLC)均可在该解码器上实现正确解析.通过对19张可变长码表的优化整合,提出一种新的码表设计方法.经验证,新码表相较使用原始码表可将硬件消耗降低30%以上.为确保整个系统设计的合理性和正确性,以RM52J为蓝本编写针对本解码器的验证器,通过对92个一致性测试码流序列解析对比,表明本设计满足AVS视频解码要求.     

H.264及AVS双模视频解码器中帧内预测的硬件设计与实现

根据H.264/AVC及AVS的特点,设计出一种适合于帧内预测解码的硬件实现方式,并根据H.264和AVS帧内预测运算上的相似性提出了基于可重构的并行结构,有利于提高解码速度,并将该结构配合其他设计好的解码器模块,在FPGA上实现了高准清晰度的H.264及AVS视频的实时解码。     

基于AVS标准的熵解码器设计

阐述了我国拥有自主知识产权的音视频编码技术标准--AVS标准的熵解码算法,介绍了基于AVS标准的熵解码器的设计.根据码流的特点划分硬件模块,采用筒形移位器结构提高解码并行性,应用Verilog硬件描述语言、EDA软件ModelSim仿真、QuartusⅡ软件综合,并通过了Altera公司的Cyclone系列FPGA芯片的下载验证,证明该设计能够实现AVS码流的实时解码功能.     

新一代多模视频解码芯片的硬件结构设计

提出了一种基于片上系统的可兼容多标准的视频解码系统结构,以满足多模解码芯片的低本设计要求,并给出了新一代多模视频解码芯片硬件结构的具体实现方案,其包含AVS、MPEG-2、MPEG-4标准的解码,此实现方案可为该多模解码器节约45%的运算单元、28%的RAM资源、86%的RAM面积以及部分Registerfile与通用电路.     

H.264高清编码器系统的设计与仿真

常用软件编码方法在用于H.264标准时,很难实现对高清视频的实时解码。为此,提出软硬件协同设计的方法,对H.264高清编码器系统进行软硬件划分及任务分配,分别设计软件部分和硬件部分。建立软硬件协同仿真环境,对整个系统的功能和性能进行仿真,采用约束随机验证的方法提高验证的功能覆盖率。仿真结果表明,该编码器系统能够对 1 024×768像素的图像帧进行编码,满足实时编码的要求。     

基于ARM的嵌入式AVS视频播放器的设计

实现了一种基于ARM处理器的嵌入式AVS视频播放器的设计方案。该方案不需添加专用的AVS视频解码芯片,仅以ARM处理器以及外围模块为硬件平台,以嵌入式Linux为操作系统,通过向MPlayer软件添加AVS视频解码库的方法,实现了AVS视频播放功能,能实时播放25f/s,分辨率为640×480的AVS视频流。     

A novel hardware/software partitioning for SIMD-based real-time AVS video decoder

Decoding high-quality videos in real-time is becoming more and more difficult with the increasing resolution. In this paper, a novel hardware/software (HW/SW) partitioning is proposed with powerful SIMD (single instruction multiple data) instructions for the real-time AVS video decoder. Since most key functions that need large amounts of computations are optimized by SIMD instead of hardware, the distribution of workload between hardware and software is balanceable, and the performance of the video decoder is improved. Besides, the generality and programmability are also maintained. The proposed method is implemented on a 32-bit dual-issue RISC processor with 256-bit vector extension. The experimental results of conformation AVS test sequences show that the video decoder system can support the real-time decoding of AVS 1080p videos at 30 fps, and improve performance over 100 times compared to the original processor without the proposed method. Moreover, this approach could be easily applied to other video decoders, such as H.264 and VC-1.     

ECC专用指令处理器软硬件协同设计

提出了一种专用指令处理器的软硬件协同设计方法,该方法可以在设计的早期阶段对处理器进行系统探索和验证.根据椭圆曲线密码算法的特点,并按照专用指令处理器的设计原则,以椭圆曲线密码运算基本操作及运算存储特性为基础,设计了超长指令字ECC专用指令处理器的指令集结构模型.根据处理器的指令集结构模型,以指令模拟器为基础,搭建了处理器的软硬件协同验证平台,从系统设计、RTL描述和FPGA硬件原型3个不同层次对处理器进行了验证.     

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).     

C高层建模设计MPEG-4解码SoC芯片

本文针对ARM946-S运用软硬件协同设计方法设计了一款低成本的MPEG-4解码系统芯片(SoC)。为了缩短验证时间和提高验证充分性,本文采用了基于C参考模型的验证方法。仿真结果表明芯片性能提升明显,针对MPEG-4 Simple Profile L3 Level最坏情况需130MHz就能实时解码。     

低速率语音编解码专用处理器设计

本文给出一种基于编码速率600bps的高质量声码器算法的专用处理器设计。介绍了语音编解码算法原理,专用处理器的体系结构,汇编器的开发和算法的移植。采用软硬件协同设计的方法,大大降低了算法的存储复杂度和运算复杂度,并在电路中验证了声码器地正确性。     

过程级动态划分的RSoC软硬件双通信模式

软硬件通信模式的选择对软硬件通信效率产生很大影响.根据硬件函数的特点,提出一种根据软硬件通信量自适应地选择通信模式的软硬件双通信模式,并构建了一种通信模式自适应决策算法,软硬件通信模式的选择对用户透明.实验表明,根据运行时系统状态自适应地选择通信模式,软硬件通信效率得到优化,面积开销也适当减少.     

Hardware/software co-design for particle swarm optimization algorithm

This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.     

Relay selection with feedback beamforming information through designed sector sweep report frame for mmWave WPANs

This paper proposes a novel relay selection strategy based on the feedback beamforming （BF） information through designed sector sweep （SSW） report frame for millimeter-wave （mmWave） wireless personal networks （WPANs）. First, an SSW report frame compatible with IEEE 802.11ad standard is designed. Second, an approach collecting instantaneous channel state information （CSI） overheard during BF is devised. Third, with the aim of minimizing the outage probability and maximizing the overall network throughput capacity, the optimal relay selection issue for non-line-of-sight （NLoS） links is formulated as a bipartite graph, and Kuhn Munkres （KM） algorithm is provided to resolve it. Both theoretical analysis and simulation results show, with CSI considering NLoS conditions and selected relays according to the overall network throughput capacity maximization principle, the improvements achieved over opportunistic relay selection strategy in terms of overall network throughput capacity and outage probability with minimal modifications to IEEE 802.1lad.     

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia system.An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning.Several parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS decoder.Also,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of REMUS.Owing to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920×1088@39fps streams when exploiting a 200 MHz working frequency.