Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.     

Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18 μm CMOS process to test the topology with a prototype global interconnect having a length of 10 mm. Power consumption of the transceiver for a data rate of 2.5 Gbps data is 2 mW. This gives an energy efficiency of 0.8 pJ/b.     

Designing fast on-chip interconnects for deep submicrometer technologies

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-μm technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator     

Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.     

Silicon oxynitride integrated waveguide for on-chip optical interconnects applications

This work explores the microfabrication technology for realizing miniature waveguide structure for on-chip optical interconnects applications. Thick oxynitride films were prepared by plasma enhanced chemical vapor deposition (PECVD) with N₂O, NH₃ and SiH₄ precursors. The composition and the bonding structure of the oxynitride films were investigated with Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS), and secondary ion mass spectroscopy. Results showed that the silicon oxynitride deposited with gas flow rates of NH₃/N₂O/SiH₄ = 10/400/10 (sccm) has favorable properties for integrated waveguide applications. The refractive index of this layer is about 1.5 and the layer has comparative low densities of O–H and N–H bonds. The hydrogen bonds can be further eliminated with high temperature annealing of the as-deposited film in nitrogen ambient and the propagation loss can be reduced significantly with thermal annealing. An integrated miniature waveguide with cross-section of 2 μm × 3 μm was realized with the proposed technology. The waveguide is able to transmit signal in either TE or TM mode with propagation loss <0.6 dB/cm (at 1550 nm) and bending radius of about 6 μm.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

SPICE compatible modelling of on-chip coupled interconnects

On-chip coupled interconnect lines are modelled using measured S-parameters. The physical consistency between single and coupled line model parameters are maintained in the proposed methodology. The SPICE compatible model is validated in both the frequency and the time domain using copper and ultra low-kappa coupled interconnects.     

Near speed-of-light signaling over on-chip electrical interconnects

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.     

高速嵌入式系统的串行互连

串行总线协议PCIe,ASI．和sRIO的比较     

Reduced delay sensitivity to process induced variability in current sensing interconnects

The effect of process induced variability in long global on-chip interconnects caused by critical dimension control and intrinsic fluctuation of transistor threshold voltage is analysed for current and voltage mode signalling. Projections in scaled CMOS technologies show that current sensing interconnects exhibit smaller mean delay and sensitivity to parameter fluctuations. The standard deviation of delay exhibits an increasing dependency on process variations at the low and high extremes of receiver to driver circuit resistance ratios. An experimental on-chip bus demonstrates the reduced delay variability in current sensing schemes.     

Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

Since the design of advanced microprocessors is based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and full-wave simulation tools for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the tradeoffs between accuracy and computation expenses for a large variety of cases     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

Skin effect of on-chip copper interconnects on electromigration

A simple model is derived to evaluate skin effect of on-chip copper interconnects on electromigration. The result gives the range of frequency in which skin effect on electromigration need to be taken into consideration.     

High-speed on-chip ECC for synergistic fault-tolerance memory chips

The placement of error-correcting-code (ECC) systems on dynamic-RAM (DRAM) chips poses many practical problems, among which are increased access time and chip size. The authors describe an optimized, self-contained, and self-timed on-chip ECC system embedded in a high-speed 16-Mb DRAM chip. This chip also has redundant word and bit lines. The combination of redundancy and on-chip ECC produces a synergistic effect which results in a major increase in fault tolerance for the hard manufacturing defects. It also improves the reliability of the chip, regardless of manufacturing defects. This improvement is attained with only a 5-ns penalty in access time and an 11% increase in chip size     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Power dissipation in microprocessors will reach a level that necessitates chip-level liquid cooling in the near future. An on-chip microfluidic heat sink can reduce the thermal interfaces between an IC chip and the convective cooling medium. Through wafer-level processing, integrated thermal-fluidic I/O interconnects enable on-chip microfluidic heat sinks with ultrasmall form factor at low-cost. This letter describes wafer-level integration of microchannels at the wafer back-side with through-wafer fluidic paths and thermal-fluidic input/output interconnection for future generation gigascale integrated chips.