半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

Degradation mechanisms of GaAs PHEMTs in high humidity conditions

We have studied the degradation mechanisms of AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) under high humidity conditions (85 °C, 85% relative humidity). The degraded samples under high humidity conditions show a decrease in maximum drain current (I_max) and a positive shift in threshold voltage (V_th). Cross-sectional transmission electron microscopy (TEM) images from the deteriorated devices reveal an existence of damaged recess surface region and a peeling of a passivation film (SiN_x). The secondary ion mass spectrometry (SIMS) depth profile at the interface between the passivation film and AlGaAs surface also indicates the diffusion of gallium (Ga), arsenic (As) and aluminum (Al) into the passivation film. The degradation of PHEMTs arises from mainly two mechanisms: (1) the positive shift in V_th due to stress change under the gate caused by the peeling of passivation films, and (2) the decrease in I_max due to the net carrier concentration reduction of the AlGaAs carrier supply layer caused by the combination of surface degradation at the AlGaAs recess regions and diffusion of Ga, As and Al at the interface between the passivation film and AlGaAs surface. A special treatment just prior to the deposition of SiN_x films on the devices effectively suppresses the degradation of PHEMTs under high humidity conditions without degradation of the high frequency performance.     

A parasitic resistance measurement method exploiting gate current–density characteristics in ultra-short Schottky-gate FETs

Gate forward current–density characteristics of ultra-short Schottky-gates are studied with experiments and calculation to clarify the mechanism of inhomogeneity in the current density along the gate length. Then, by exploiting the gate current–density characteristics, a new DC measurement method is proposed to evaluate the parasitic source and drain resistances, R_s and R_d, in the Schottky-gate FETs. The method is based on a gate-probing end-resistance technique, which can evaluate the values R_s and R_d simply and accurately by using DC measurement, even if the device has an ultra-short gate length L_g of less than 0.15 μm, because it applies a bias larger than a built-in voltage V_bi of the Schottky junction to the gate electrode in order to eliminate inhomogeneities in the gate current–density characteristics.     

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd

Hot-carrier degradation of n-MOSFETs at high gate voltages (V_g=V_d) is examined. A new lifetime prediction method is developed based on the universal power law between the degradation of saturated drain current (dI_dsat) and the product of the injected charge fluence times the gate current, which is independent of gate or drain voltages. This method is applied to 4 and 5 nm n-MOSFETs and lifetimes are estimated under their operation conditions. It is applicable to n-MOSFETs with ultrathin gate oxides.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.     

GaAs中的低温Zn扩散

本文研究了低温条件下Zn向GaAs中的扩散。实验是用ZnAs2源在抽真空的石英管中进行的。研究了结深Xj,扩散温度T和扩散时间t的关系。结果表明,表面层电阻Rs随Xj,的增加而降低;表面浓度Cs随1/T的增加而降低;迁移率随Cs的增加而降低。将Cs对1/(RsXj)作图表明,Cs随1/(RsXj)的增加而增加。这一关系可作为判断多层GaAlAs/GaAs外延层扩Zn后表面浓度的简便方法。文中讨论了Zn在GaAs和InP中的扩散机理,比较了Zn在InP和GaAs扩散层中的参数。 该扩散工艺可获得表面光亮、无损伤的高浓度表面层,并已在GaAs/Ga1-xAlxAs双异质结发光管的制备工艺中应用。制得了光输出功率为24mW、串联电阻为35、压降为2.4V的GaAs/Ga1-xAlxAs双异质结发光管。     

Two-stage hot-carrier degradation behavior of 0.18 μm 18 V n-type DEMOS and its recovery effect

Hot-carrier degradation of 18 V n-type drain-extended MOSFETs (DEMOS) is carefully investigated in this work. Two-stage degradation behavior and apparent recovery effect on the removal of the stress are observed. The first stage of the degradation is found to be mainly due to an increase of the drain series resistance (R_d), which results from the electron trapping in the drift region oxide. The degradation of R_d becomes saturated in the second stage, and the reduction of the carrier mobility in the channel begins to be dominated. In addition, recovery effect has been proved to origin from the decrease of R_d, and a new trapping-detrapping model is proposed to well describe the recovery effect in DEMOS.     

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density (J_E) and impact ionization generation rate (R_II) distributions in the devices. The high R_II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.     

The diffusion of Zn in GaAs at low temperature

The diffusion of Zn into GaAs at low temperature has been investigated. The experiments are carried out in an evacuated and sealed quartz ampoule using ZnAs₂ as the source of Zn. The relation among the junction depth (X _j), the time (t) and the temperature (T) of diffusion has been investigated. It is found that the sheet resistance (R _s) of diffusion layer increases asX _j decreases. The surface concentration (C _s) decreases as 1/T increases, and mobility (μ) decreases asC _s increases. TheC _s versus 1/X _j·R_s) are plotted, the results are thatC _s increases as 1/X _j ·R _s ) increases. This is a simple method for determiningC _s of the multiple GaAs/GaA1As epitaxial layer. The mechanism of Zn diffusion in GaAs and InP is discussed. This process has been applied to fabricate GaAs/GaAlAs double heterojunction light emitting diodes and an output power of 2—4mW is obtained, the series resistance is 3—5Q.     

Performance and optimisation of dual material gate short channel BULK MOSFETs for analogue/mixed signal applications

The challenge of analogue operation of CMOS devices and its parameters is a very important study for future technologies. In this article, the performance of dual material gate bulk MOSFETs for analogue/mixed signal applications is explored. Moreover, the optimisation of the device is done based on the variation of length and work-function difference of the two gate metals. The effect of drain induced barrier lowering in this structure is studied in detail. Moreover the different analogue parameters such as transconductance (g _m), output resistance (R _o) tuning for high performance of the device are also investigated by extensive simulations.     

Degradation of d.c. parameters in enhancement mode WNx self-aligned gate GaAs MESFETs under high temperature stress

The effect of thermal stress on the d.c. parameter degradation of enhancement mode tungsten nitride (WN_x) self-aligned gate GaAs MESFETs was investigated. Threshold voltage, source-drain current and transconductance were measured during the tests. The physical properties of the device after thermal stress were analyzed by means of Auger electron spectroscopy (AES), X-ray diffractometry to identify the degradation mechanism. The d.c. failure mode consists of an increase in the threshold voltage and a decrease in the current and transconductance of the FETs. The device simulator was also used for analytical understanding of the d.c. parameter degradation. The simulated results showed that d.c. parameter degradation was mainly attributed to the increase in source and drain ohmic contact resistances. From the AES analysis, we found that the increase of contact resistance was due to carrier compensation, which was caused by Ga outdiffusion and Ni indiffusion under the ohmic contact layer. Therefore the thermally activated carrier compensation effects by trap generation are proposed to be the main failure mechanism for d.c. parameter degradation of enhancement mode WN_x self-aligned gate GaAs MESFETs.     

Accurate series resistance measurement of solar cells

The series resistance (R_s) of a solar cell is commonly represented as a constant resistance value. However, because of the distributed nature of series resistance, the effective lumped R_s vary with current density and illumination intensity. Treating R_s as a constant is usually insufficient for an accurate analysis of its J–V curve. This work first presents a review of the distributed nature of series resistance and commonly applied methods to measure R_s. Particular attention is given to the multi‐light method (MLM) and it is discussed in detail, where R_s in both the light and dark can be measured as a function of current by extracting R_s from a set of current–voltage (J–V) curves attained at different illumination intensities. The principle behind this method is discussed, and the results are then compared with those of other known methods of R_s measurement. The accurate measurement of R_s(J) attained with the MLM permits the extraction of an R_s‐corrected J–V curve, which is theoretically more accurate than that attained by alternative methods because of negligible error from injection dependence and spectral mismatch. With the solar cell equation modified to include R_s(J), we attain a much better fit to experimental data, finding a significant reduction in error compared with using a constant R_s. Copyright © 2011 John Wiley & Sons, Ltd.     

Efficiency Enhancement in Organic Photovoltaic Cells: Consequences of Optimizing Series Resistance

Here, means to enhance power conversion efficiency (PCE or η) in bulk‐heterojunction (BHJ) organic photovoltaic (OPV) cells by optimizing the series resistance (R_s)—also known as the cell internal resistance—are studied. It is shown that current state‐of‐the‐art BHJ OPVs are approaching the limit for which efficiency can be improved via R_s reduction alone. This evaluation addresses OPVs based on a poly(3‐hexylthiophene):6,6‐phenyl C₆₁‐butyric acid methyl ester (P3HT:PCBM) active layer, as well as future high‐efficiency OPVs (η > 10%). A diode‐based modeling approach is used to assess changes in R_s. Given that typical published P3HT:PCBM test cells have relatively small areas (～0.1 cm²), the analysis is extended to consider efficiency losses for larger area cells and shows that the transparent anode conductivity is then the dominant materials parameter affecting R_s efficiency losses. A model is developed that uses cell sizes and anode conductivities to predict current–voltage response as a function of resistive losses. The results show that the losses due to R_s remain minimal until relatively large cell areas (>0.1 cm²) are employed. Finally, R_s effects on a projected high‐efficiency OPV scenario are assessed, based on the goal of cell efficiencies >10%. Here, R_s optimization effects remain modest; however, there are now more pronounced losses due to cell size, and it is shown how these losses can be mitigated by using higher conductivity anodes.     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

A Comparative Study of a Dielectric‐Defined Process on AlGaAs/InGaAs/GaAs PHEMTs

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric‐defined process. This process was utilized to fabricate 0.12 μm × 100 µm T‐gate PHEMTs. A two‐step etch process was performed to define the gate footprint in the SiN_x. The SiN_x was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T‐gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross‐sectional area of the gate and its mechanically stable structure. From s‐parameter data of up to 50 GHz, an extrapolated cut‐off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiN_x) with sample A (dry etching for the SiN_x), we observed an 62.5% increase of the cut‐off frequency. This is believed to be due to considerable decreases of the gate‐source and gate‐drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.     

Enhanced Performance of Fullerene n‐Channel Field‐Effect Transistors with Titanium Sub‐Oxide Injection Layer

Enhanced performance of n‐channel organic field‐effect transistors (OFETs) is demonstrated by introducing a titanium sub‐oxide (TiO_x) injection layer. The n‐channel OFETs utilize [6,6]‐phenyl‐C₆₁ butyric acid methyl ester (PC₆₁BM) or [6,6]‐phenyl‐C₇₁ butyric acid methyl ester (PC₇₁BM) as the semiconductor in the channel. With the TiO_x injection layer, the electron mobilities of PC₆₁BM and PC₇₁BM FET using Al as source/drain electrodes are comparable to those obtained from OFETs using Ca as the source/drain electrodes. Direct measurement of contact resistance (R_c) shows significantly decreased R_c values for FETs with the TiO_x layer. Ultraviolet photoelectron spectroscopy (UPS) studies demonstrate that the TiO_x layer reduces the electron injection barrier because of the relatively strong interfacial dipole of TiO_x. In addition to functioning as an electron injection layer that eliminates the contact resistance, the TiO_x layer acts as a passivation layer that prevents penetration of O₂ and H₂O; devices with the TiO_x injection layer exhibit a significant improvement in lifetime when exposed to air.     

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L₁) for a given gate length (L) are also studied and the optimum lengths L₁ under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.     

Highly Efficient Rapid Annealing of Thin Polar Polymer Film Ferroelectric Devices at Sub‐Glass Transition Temperature

An unexpected rapid anneal of electrically active defects in an ultrathin (15.5 nm) polar polyimide film at and below glass transition temperature (T_g) is reported. The polar polymer is the gate dielectric of a thin‐film‐transistor. Gate leakage current density (J_g) through the polymer initially increases with temperature, as expected, but decreases rapidly at T_g ? 60 °C. After ≈2 min at T_g, the leakage is reduced by nearly three orders of magnitude. A concomitant observation is that the drain current (I_d)–gate voltage (V_g) hysteresis decreases with temperature, reaching zero at nearly the same temperature at which J_g collapses. As J_g drops further, the drain current hysteresis increases again but in the opposite direction. This combination strongly supports the interpretation of rapid defect annealing.