Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

CMOS集成电路的ESD设计技术

首先论述了CMOS集成电路ESD保护的必要性 ,接着介绍了CMOS集成电路ESD保护的各种设计技术 ,包括电流分流技术、电压箝位技术、电流均衡技术、ESD设计规则、ESD注入掩膜等。采用适当的ESD保护技术 ,0 8μmCMOS集成电路的ESD能力可以达到 30 0 0V。     

TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, V_t1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

A thyristor-only input ESD protection scheme for CMOS RF ICs

We propose an input protection scheme composed of thyristor devices only avoiding usage of a clamp NMOS device to minimize the area consumed by an input pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device in the input pad. The comparison study mainly focuses on robustness against the human body model electrostatic discharge (HBM ESD) in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices, and by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness

New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout.     

亚微米CMOS集成电路的ESD保护新结构

本文主要介绍几种新型的ESD保护结构,包括互补SCR结构,双寄生SCR结构,低触发电压,高触发电流的横向SCR结构等,利用这些结构可以对CMOS集电路的输入／输出进行有效地ESD保护。     

RC-SCR: very-low-voltage ESD protection circuit in plain CMOS

A simple, novel RC-coupled very-low-voltage silicon controlled rectifier, electrostatic discharge protection circuit is reported, implemented in 0.35 μm CMOS, which is confirmed by transient electrostatic discharge simulation and measurement, and results in a very low triggering of 7 V, a 60% reduction over traditional silicon controlled rectifiers     

Lateral SCR devices with low-voltage high-current triggeringcharacteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6×60 μm² in a standard 0.6-μm CMOS technology without extra process modification     

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again.     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies     

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.     

一种抑制ESD保护电路闩锁效应的版图研究

针对具有低压触发特性的静电放电(electrostatic discharge,ESD)保护电路易闩锁的不足,本文结合CSMC0.6μm CMOS工艺,设计了一种可应用于ESD保护电路中的独立双阱隔离布局方案,这种方案不仅可以有效的阻断形成闩锁的CMOS器件固有纵向PNP与横向NPN晶体管的耦合,且兼容原有工艺而不增加版图面积。将此布局方案与常规保护环结构同时应用于笔者研制的具有低压快速触发特性双通路ESD保护电路中,通过流片及测试对比表明,该布局方案在不影响保护电路特性的同时,较常规保护环结构更为有效的克服了保护电路的闩锁效应,从而进一步提升了该保护电路的鲁棒性指标。本文的布局方案为次亚微米MOS ESD保护电路版图设计提供了一种新的参考依据。     

一种用于输出引脚的新型静电防护结构

Electro-static discharge(ESD)is always a serious threat to integrated circuits.To achieve higher robustness and a smaller die area at the same time,a novel protection structure for the output pad is proposed.The complementary SCR devices in this structure can protect not only the output under positive or negative stresses versus VDD or VSS,respectively,but also the power rails at the cost of almost no extra area.The robustness of the proposed structure is about three times higher than the conventional four-finger GGNMOS/GDPMOS structure in the same area condition.     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.