在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Ni(OH)2及Co(OH)2片状纳米晶体的合成与表征

使用强碱氢氧化钾为沉淀剂,通过水热法成功合成了具有六角形貌的过渡金属氢氧化物Ni(OH)2及Co(OH)2片状纳米晶.利用X射线粉末衍射仪和透射电子显微镜对样品的结构和形貌进行了表征.透射电镜观察结果显示Ni(OH)2相为规则六角纳米片,Co(OH)2相为纳米片和纳米棒的混合物.选区衍射结果指出Ni(OH)2及Co(OH)2纳米晶体均为单晶体.Ni(OH)2及Co(OH)2纳米片的产率分别达到了70%和90%.将实验结果同前人的过渡族金属氢氧化物纳米片报道进行了比较,提出了一个新的片状纳米晶的形成机制,指出在正常的沉淀条件下,Ni(OH)2及Co(OH)2纳米晶的稳定形貌总为六角片状.     

Effects of nitrogen annealing on electron scatterings in SiSiO2 interface

The effective mobility of electrons at Si (100) surfaces was measured as a function of electron density N_s = 5 × 10¹¹?1 × 10¹³ cm^?2 at 4.2K for samples with and without annealing (10 min–2 hr) in nitrogen gas at 1000°C after wet thermal oxidation. A great part of the scattering by Coulomb and short-range potentials was reduced by a short (～10 min) anneal time, although the subsequent annealing resulted in a slight increase in the number of the scatterers. On the other hand, scattering by a surface roughness potential was reduced with increase in the anneal time. These scattering effects associated with N₂ annealing are discussed.     

Characterization of crystalline MOCVD SrTiO3 films on SiO2/Si(100)

SrTiO₃ thin films (STO), were deposited on Si(100) covered by 2 nm of SiO₂, at different temperatures from 450 °C to 850 °C using liquid injection MOCVD, the bimetallic precursor being Sr₂Ti₂(OiPr)₈(tmhd)₄. The STO films were analysed by XRD, FTIR, SIMS and TEM. An amorphous layer was observed between STO and SiO₂/Si. The nature and thickness of the interlayer were determined, as well as the most favourable conditions for a good quality crystalline STO film, and a reduced interlayer.     

TiO_2/SiO_2、ZrO_2/SiO_2多层介质膜光学损耗及激光损伤研究

以TiO_2/SiO_2及ZrO_2/SiO_2多层介质膜为例,测试了不同工艺条件及不同膜系结构下薄膜样品的光学损耗及激光损伤阈值,同时对实验结果作了初步的分析讨论.     

Effect of H2 content on reliability of ultrathin in-situsteam generated (ISSG) SiO2

This letter demonstrates the effect of H₂ percentage during oxidation on the quality of the in-situ steam generated (ISSG) oxide. Our results indicate the reliability of ISSG oxide is considerably improved as the H₂ percentage increases, from the viewpoint of stress-induced leakage current (SILC) and charge-to-breakdown (Q_BD). Such enhanced reliability of the ISSG oxide may be explained by the reduction of defects in the SiO₂ network within the structural transition layer, such as Si dangling bonds, weak Si-Si and strained Si-O bonds, by highly reactive oxygen atoms which are hypothesized to be dissociated from the molecular oxygen due to the presence of hydrogen     

Reliability of a connected-(r1, s1)-or-(r2, s2)-or-..-or-(rk, sk)-out-of-(m,n): F lattice system

A (linear or circular) connected-(r₁, s₁)-or-(r₂, s₂)-or-^{. .}-or-(r_k, s_k)-out-of-(m, n): F lattice system is the (linear or circular) (m, n)-lattice system if the system fails whenever all components in a connected-(r₁, s₁)-submatrix or all components in a connected-(r₂, s₂)-submatrix or ^{. .} or all components in a connected-(r_k, s_k)-submatrix fail. This paper presents a recursive algorithm for the reliability of the (linear or circular) connected-(r₁, s₁)-or-(r₂, s₂)or-^{. .}-or-(r_k,s_k)-out- of-(m, n):F lattice system. The recursive algorithm requires time and time in the linear case and the circular case, respectively Furthermore, we can reduce the more computing time in the statistically independent and identically distributed case or considering some special systems. Especially, the closed formula is given for the reliability of the linear connected-(2, 1)-or-(1, 2)-out-of-(m, 2): F lattice system in the statistically independent and identically distributed case.     

SiO2/CeO2混合磨料对硅CMP效果影响

以获得高去除速率和低表面粗糙度为目标,建立了基于纳米氧化铈-硅溶胶复配混合磨料新模式。采用小粒径、低分散度的30 nm氧化铈-硅溶胶复配混合作为磨料,利用氧化铈对硅片表面化学反应产物硅酸胺盐的强络合作用,加快了硅衬底表面化学反应进程。分析了复合磨料抛光的机理,通过Aglient 5600LS原子力显微镜,测试了抛光前后的厚度及抛光后的硅片表面微粗糙度。实验结果表明,复合磨料抛光后硅片表面在10μm×10μm范围内粗糙度方均根值0.361 nm,表面微粗糙度降低16%以上,去除率为1 680 nm/min,硅CMP速率提高8%以上,实现了高去除速率、低表面粗糙度的硅单晶抛光。     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Evaluation of Qbd for electrons tunneling fromthe Si/SiO2 interface compared to electron tunneling from thepoly-Si/SiO2 interface

Electrical time-to-breakdown (TTB) measurements have shown the charge to breakdown Q_bd of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. Here the authors correlate the higher n-well Q_bd to smooth capacitor oxide/substrate interfaces and minimized grain boundary cusps at the poly-Si gate/oxide interfaces, confirming that Fowler-Nordheim tunneling is the dominant current conduction mechanisms through the oxide. They correlate higher Q_bd to higher barrier height for a given substrate type and observe that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. This is attributed to surface roughness at the poly-Si gate/SiO₂ interface. A poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and allow higher Q_bd to be achieved     

非晶态SiO2过渡层对生长C轴取向LiNbO3薄膜的影响

采用磁控溅射方法,在Si衬底和LiNbO3薄膜之间引入SiO2过渡层制备LiNbO3薄膜。采用X射线衍射（XRD〉、傅里叶变换红外吸收光谱（FT-IR）和扫描电子显微镜（SEM）对LiNbO3薄膜的结晶取向、组成成分和表面形貌进行了表征,重点研究了非晶态SiO2过渡层对LiNbO3薄膜C轴取向的影响。结果表明,非晶态S...     

Theoretical and measured characteristics of metal(CoSi2)-insulator(CaF2) resonant tunnelingtransistors and the influence of parasitic elements

We report on the theoretical and measured characteristics of triple-barrier metal (CoSi₂)-insulator(CaF₂) (M-I) resonant tunneling transistors (RTT) grown on an n-Si(111) substrate, and the influence of their parasitic elements on the measured characteristics. First, we analyze theoretical characteristics of an M-I RTT, and then show fabrication process and current-voltage (I-V) characteristics obtained at 77 K, in which several degradations are observed: large resonance voltage, low peak-to-valley (P-V) ratios at negative differential resistance (NDR), and reverse base current. Analysis, taking several parasitic elements (e.g., base resistance, substrate resistance and leakage currents connected to the intrinsic transistor) into account, explains observed characteristics well. Finally, we show the first transistor action with large P-V ratios at 300 K, which is achieved by reducing collector-emitter leakage currents     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO₂进行干法刻蚀, 研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系, 这为如何获得垂直的刻蚀侧壁提供了参考。     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO2进行干法刻蚀,研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系,这为如何获得垂直的刻蚀侧壁提供了参考。     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.