Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard

This paper presents a testing scheme for analog and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. A high-speed dynamic current sensor is described, as well as an innovative self-diagnostic method called VDDQ. The former is used to measure signature supply currents and to compare them with the footprint of a defect-free circuit. The latter senses the quiescent nodal voltages on several nodes of the circuit under test and compares them to their nominal values. A flag is raised if significant deviations are found. Simulation results are provided for the high-speed dynamic current sensor. Through simulations the VDDQ method has performed at one node test every half millisecond and has potential for much higher speed. It is faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defect-free IC to enter the market in significantly less time than with conventional testing methods.     

一种混合信号边界扫描测试系统的设计

IEEE 1149.4的推出为混合信号测试提供了一个标准,推动了混合信号边界扫描测试技术的研究。简要介绍了IEEE 1149.4标准及混合信号测试方法,并根据标准定义的测试结构设计出一种混合信号边界扫描测试系统。经过测试验证,该系统能够对混合信号电路进行互连测试和参数测试,可实现准确的故障诊断,具有一定的实用价值。     

IEEE 1149.4标准实验测试结构设计和扩展研究

本文采用复杂可编程逻辑器件（CPLD）和分立器件,设计实现了IEEE 1149.4混合信号边界扫描标准实验测试结构。为了提高互连测试的故障诊断能力,文中对模拟边界模块（ABM）开关结构进行了一些修改。针对ABM单元的这些修改允许测试者可以将模拟输入信号与多个电压进行比较。当测试者在简单互连或扩展互连中遇到桥接故障,扩展的ABM开关结构使得故障更容易探测。     

Methods of Testing Discrete Semiconductors in the 1149.4 Environment

This paper describes measurement methods for testing discrete semiconductors in the environment defined by the IEEE 1149.4 standard for a mixed-signal bus. First, the paper introduces and illustrates measurement procedures for obtaining such essential electrical parameters of diodes and transistors as can be used for testing and identification. Then, the procedures are carried out and the achieved measurement results presented. To demonstrate the usability of the measurement procedures, the paper then presents test methods and measurement results for discrete component blocks. The results indicate that testing and measuring some of the electrical parameters of discrete semiconductors is possible in the 1149.4 environment. These parameters allow the determination of whether the component under test is working properly or not. Our tests only covered the semiconductors’ DC features, disregarding their AC features. Also discussed are limitations of the 1149.4 environment in discrete semiconductor testing.

混合信号电子产品的自动测试技术

电子产品微型化使自动测试成为必然,而边界扫描技术则使自动测试成为可能。文章分析了1149.4和1149.1标准的测试访问端口,以及测试逻辑结构和测试协议的异同,提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型;在此基础上,详细阐述了两个标准在混合信号电子产品自动测试中的综合应用方法;最后,以典型的混合信号电路D/A转换器为例,对两个标准的综合应用进行了仿真验证。     

混合信号集成电路边界扫描测试技术的实现

IEEE1149.4为混合信号的测试提供了一项标准,同时也提供了一种重要的可测试性设计（DFT）技术,该技术不仅可以测试芯片或PCB之间的管脚连接是否存在故障,还可以测试芯片的逻辑功能。本文以IEEE1149.4标准为基础,结合混合信号边界扫描测试系统进行了测试验证,完成对混合信号电路的参数测试。     

Overview of the MPEG Reconfigurable Video Coding Framework

Video coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis.     

IEEE1149.4模拟和混合信号测试总线标准

模拟和混合信号边界扫描标准(IEEE1149.4)是针对电路板级外部分立元件的测试而发展起来的,该标准与IEEE1149.1兼容,另外,在此基础上,IEEE1149.4又增加了两根线,用来控制模拟信号.目前1149.4的标准,不但应用在传统的电路板上,在混合信号集成电路甚至包含混合信号的SoC系统芯片上,都有应用.本文...     

Goodness-of-fit tests based on spacings for progressively type-II censored data from a general location-scale distribution

There has been extensive research on goodness-of-fit procedures for testing whether or not a sample comes from a specified distribution. These goodness-of-fit tests range from graphical techniques, to tests which exploit characterization results for the specified underlying model. In this article, we propose a goodness-of-fit test for the location-scale family based on progressively Type-II censored data. The test statistic is based on sample spacings, and generalizes a test procedure proposed by Tiku . The distribution of the test statistic is shown to be approximated closely by a s-normal distribution. However, in certain situations it would be better to use simulated critical values instead of the s-normal approximation. We examine the performance of this test for the s-normal and extreme-value (Gumbel) models against different alternatives through Monte Carlo simulations. We also discuss two methods of power approximation based on s-normality, and compare the results with those obtained by simulation. Results of the simulation study for a wide range of sample sizes, censoring schemes, and different alternatives reveal that the proposed test has good power properties in detecting departures from the s-normal and Gumbel distributions. Finally, we illustrate the method proposed here using real data from a life-testing experiment. It is important to mention here that this test can be extended to multi-sample situations in a manner similar to that of Balakrishnan et al.     

Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits

A traditional specification-based core-level test method is no longer attractive in testing deeply embedded analog and mixed-signal circuits due to limited accessibility and resource issues. In order to overcome such difficulties, loopback testing has been considered as a promising solution when circuits include data conversion units; however its widespread adoption has been hindered due to fault masking, which may cause serious yield loss and test escape. The combination of seriously degraded components in a signal path and overqualified components in another signal path, may result in the overall performance of the loopback path being completely fault-free. This paper presents an efficient loopback test methodology which provides test accuracy equivalent to a traditional specification-based test. In our approach, a traditional loopback scheme is re-configured with an analog filter and an adder implemented on a Device Interface Board (DIB), and a multiple tone input is applied to the DUTs. The outcome of the proposed test is a set of performance parameters, allowing the evaluation of DUTs with respect to its specification, and efficient guidance of a self-repair mechanism. The mathematical analysis for the fault masking problem, based on linearity and noise parameters, is provided. In addition, various design parameters which may impact the accuracy of the proposed method are investigated. Both simulation and hardware measurements are presented to validate the proposed technique.     

The problem of size [EMC testing]

Some systems, such as telephone exchanges, are simply too large or too complex to undergo EMC testing in the normal way. Three main problems exist with the EMC Directive for large systems. First, the size of the open area test sites recommended in existing standards is often too small for large systems. Secondly, there is a requirement to vary the position of the cables attached to the equipment under test (EUT) to maximise emissions. Finally, standards require the rotation of the equipment under test to maximise the emissions measured. This would prove difficult in the case of a physically large system and its associated cabling. The limitations of existing standards has been recognised by the European telecoms industry, and a new standard covering the measurement of emissions from large telecoms systems has been published. This standard is ETS 300 127 (1994), published by the European Telecommunications Standards Institute (ETSI), and it may be used to demonstrate compliance to the EMC Directive     

10 A～2 kA智能化浪涌电流测试仪

介绍了整流二极管智能化浪涌电流测试仪的技术指标和工作原理,以及依照中国整流二极管浪涌电流测试的国家标准,并为适应国外厂商对该指标的特殊要求,由单片机及D/A和A/D转换器组成智能化控制系统。介绍了两种浪涌电流波形的产生、波形的个数、浪涌电流值的设置,并对被测整流二极管经浪涌电流测试后的实际电流波形和电流值等技术参数进行设计、检测和数据处理,在仪器面板上以数字显示出实际浪涌电流值,最后提供了测试方法及误差分析。实践证明,它是一种测量整流二极管有关技术参数的经济实用的新一代专用测试仪器,已获得实际应用。     

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.     

Probabilistic testing of OSI protocols

Protocols are large and complex software systems. Complete conformance testing of an implementation against its standard may not be feasible in terms of the resources available. This paper discusses a new approach, the P-method, to the testing of meaningful subsets of communication protocols for an asynchronous model of communication. The approach is based on the probabilistic verification of protocols, which is carried out on the more probable part of the protocol first. The technique can be used for generating probabilistic test sequences for the conformance testing of communication protocols to standards. The proposed method yields meaningful protocol test sequences which test the most probable behaviors of a protocol when the testing of the complete protocol is not feasible. Probabilistic test sequences can be categorized into different classes. The higher the class a probabilistic test sequence is in, the larger the extent of the protocol it covers, and the better is the fault coverage. If the class of a test sequence is high enough, its fault coverage is comparable to the fault coverage of test sequences generated by other methods. Results from a study of the P-method, using alternating bit protocol (ABP) and a subset of NBS TP4 as examples, support the claims above. It can also be shown that if errors are introduced only to the more probable part of the protocol, the fault coverage of P-method is also comparable to other methods     

Counterfeit Integrated Circuits: Detection,Avoidance, and the Challenges Ahead

The counterfeiting of electronic components has become a major challenge in the 21st century. The electronic component supply chain has been greatly affected by widespread counterfeit incidents. A specialized service of testing, detection, and avoidance must be created to tackle the worldwide outbreak of counterfeit integrated circuits (ICs). So far, there are standards and programs in place for outlining the testing, documenting, and reporting procedures. However, there is not yet enough research addressing the detection and avoidance of such counterfeit parts. In this paper we will present, in detail, all types of counterfeits, the defects present in them, and their detection methods. We will then describe the challenges to implementing these test methods and to their effectiveness. We will present several anti-counterfeit measures to prevent this widespread counterfeiting, and we also consider the effectiveness and limitations of these anti-counterfeiting techniques.     

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies

The conventional practice for testing analog or RF integrated circuits is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring them directly. In this paper, we perform efficiency evaluation of this strategy, and in particular we perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is evaluated in terms of model accuracy by using classical metrics such as average and maximal prediction errors, and in terms of prediction reliability by introducing a new metric called Failing Prediction Rate (FPR). Results are illustrated on two case studies for which we have experimental test data.     

Recurrent pattern matching based stereo image coding using linear predictors

The Multidimensional Multiscale Parser (MMP) is a pattern-matching-based generic image encoding solution which has been investigated earlier for the compression of stereo images with successful results. While first MMP-based proposals for stereo image coding employed dictionary-based techniques for disparity compensation, posterior developments have demonstrated the advantage of using predictive methods. In this paper, we focus on recent investigations on the use of predictive methods in the MMP algorithm and propose a new prediction framework for efficient stereo image coding. This framework comprises an advanced intra directional prediction model and a new linear predictive scheme for efficient disparity compensation. The linear prediction model is the main novelty of this work, combining adaptive linear models estimated by least-squares algorithm with fixed linear models provided by the block-matching algorithm. The performance of the proposed intra prediction and disparity compensation methods when applied in an MMP encoder has been evaluated experimentally. Comparisons with the current stereo image coding standards showed that the proposed MMP algorithm significantly outperforms the Stereo High Profile of H.264/AVC standard. In addition, it presents a competitive performance relative to the MV-HEVC standard. These results also suggest that current stereo image coding standards may benefit from the proposed linear prediction scheme for disparity compensation, as an extension to the omnipresent block-matching solution.     

On trends in automatic testing of analog circuits

The rapid change and the turmoil characteristic of the electronics industry today, is evident also in analog testing field. Because an analog electronic circuit or device may be tested many times during its life-time, analog testing has become a significant component of life cycle cost. In this paper, we discuss briefly the emerging trends towards test techniques; testlanguages; test system architectures; test instruments; test computers; and test requirements as related to analog testing field. The topics discussed assume a new importance, however, as VLSI introduces more analog circuits into the digital domain.     

Self-convergent scheme for logic-process-based multilevel/analog memory

A multilevel/analog electrically erasable programmable read only memory cell fabricated by standard CMOS logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE subcircuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.     

功率VDMOS稳态热阻测试的关键影响因素

热阻值是衡量功率VDMOS器件热性能优劣的重要参数,但在实际的热阻测试过程中,诸如测试电流、延迟时间、壳温控制等因素都会对测试结果造成直接的影响。因此,测试时应当深入理解和分析各种影响因素,依据严格的测试标准灵活的使用测试设备,以达到较高的测试精度和重复性。按照稳态热阻测试的步骤,详细论述了影响其测试结果的关键因素,并提出较为准确的修正方法,设计了针对性试验对其进行了验证。试验表明,该测试方法实现了较为精确的稳态热阻测量,可为功率VDMOS热阻测试标准的制定提供参考和借鉴。