Modeling of the MOSFET inversion charge and drain current, inmoderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model     

Harmonic and intermodulation performance of moderate inversion MOSFET transconductors

This article discusses the harmonic and intermodulation performance of moderate inversion MOSFET transconductors. The bulk of the nMOS transistor is tied to ground, at all levels of inversion, including moderate inversion and the transistor is operating in the saturation region where it behaves qualitatively as a constant current source. The current–voltage characteristic of the transistor is approximated using a Fourier-series model. Using this model, analytical expressions are obtained for amplitudes of the harmonics and intermodulation products resulting from multi-sinusoidal gate-to-source input voltages. The special case of a two equal-amplitude sinusoidal input is considered in detail and the results are compared with previously published results.     

High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design

High frequency (HF) distortion of MOSFETs has been characterized at different frequencies and bias conditions with a single tone measurement system. The results show that a MOSFET has much higher "low frequency limit" (LFL) than a bipolar transistor with similar critical dimensions, implying that the HF distortion characteristics of MOSFETs operating at a frequency lower than LFL is dictated by its low-frequency behavior. This discovery is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. It has also been found that the second harmonic P/sub f2/ reaches to its minimum as f/sub T/ peaks, due to a similar nonlinearity cancellation as in bipolar transistors. Furthermore, the measured data shows fairly constant distortion characteristics over a wide range of drain biases as the device operates in the saturation region. Simulation with a BSIM3v3-based sub-circuit model demonstrates that the distortion behavior of MOSFETs can be well predicted by an RF model if it can accurately describe both dc and ac characteristics with proper parameter extraction. Sensitivity of the distortion on various physical effects, such as the mobility degradation, velocity saturation, channel length modulation, and drain-induced barrier lowering, are also studied to provide insights of the key nonlinearity variation contributors from a practical modeling point of view.     

“Sweet Spots” in Moderate Inversion for MOSFET Squarer Transconductors

Two "sweet spots" are analytically identified to enable MOSFET squarer differential transconductors to efficiently operate in moderate inversion. Measurements at low frequencies demonstrate the practicality of using moderate inversion when input signals are limited to about 200 mV_pk-pk. At the first sweet spot, very low distortion of significantly less than 0.5% total harmonic distortion is possible. For comparison, the sweet spot for the third harmonic is shown for the linear differential transconductor. This brief also discusses the effect of the variations in threshold voltage on the location of the sweet spots, and demonstrates that this sensitivity can be greatly reduced using an appropriate biasing circuit. The proposed approach is of particular interest for low voltage and low current squarer transconductance applications.     

Consistent noise models for analysis and design of CMOS circuits

Simple, physics-based MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series-parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level concept are developed. The proportionality between the flicker noise corner frequency and the transistor transition frequency is proved and experimentally verified under wide bias conditions. Application of the noise models to a low-noise design is shown.     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

A seeded-channel silicon-on-insulator (SOI) MOS technology

An improved silicon-on-insulator (SOI) MOSFET transistor structure is presented. The structure retains the density and low-capacitance advantages of SOI, but places the transistor channel region in the single-crystal silicon substrate. This "seeded-channel" configuration avoids floating-body effects and ensures that defects in the SOI will not affect the channel mobility. The technology has been used to successfully fabricate n-channel transistors.     

An explicit analytical charge-based model of undoped independent double gate MOSFET

This paper describes an explicit analytical charge-based model of an undoped independent double gate (DG) MOSFET. This model is based on Poisson equation resolution and field continuity equations. Without any fitting parameter or charge sheet approximation, it provides explicit analytical expressions of both inversion charge and drain current considering long undoped transistor. Consequently, this is a fully analytical and predictive model allowing describing planar DG MOSFET as well as FinFET structures. The validity of this model is demonstrated by comparison with Atlas simulations.     

伯克利短沟道绝缘栅场效应晶体管模型的研究进展

随着金属氧化物半导体(MOS)集成电路工艺的飞速发展,体硅金属氧化物半导体场效应晶体管(MOSFET)模型经历了从物理到经验,最后到半经验物理的转变.介绍了以阈值电压和反转电荷为建模基础的伯克利短沟道绝缘栅场效应晶体管模型(BSIM),以及该模型中阈值电压、饱和电流和电容的基本建模理论.回顾了近年来体硅MOSFET BSIM的研究进展,着重从各种模型的优缺点、建模机理和适用范围方面分析了4种最有代表性的BSIM,即BSIM3v3,BSIM4,BSIM5和BSIM6.从模型的发展历史可以看出模型是随着MOSFET尺寸的缩小而不断完善和发展的.最后,对体硅MOSFET的模型发展趋势进行了展望.     

Measurements of leakage currents and the capacitance of the storagecapacitor in a single DRAM cell

Methods of measuring leakage currents and the capacitance of the storage capacitor in a single DRAM cell have been developed for correlation with the electrode shape of the capacitor. In the circuit used for these measurements, the plate electrode of the storage capacitor is connected to the gate of the MOSFET which amplifies the voltage variations of the storage capacitor during the measurements. Here, only a conventional transistor parameter analyzer and a capacitance meter are required for the measurements. For the capacitance measurement, the linear region characteristics of the MOSFET are used to simplify the analysis. For the leakage current measurement, however, the subthreshold region characteristics of the MOSFET are used to enhance the accuracy of the measurement. The results show that the very low leakage currents (down to below 0.1 fA) and the capacitance (37.5 fF) of the storage capacitor can be measured accurately. Further, the leakage current-voltage characteristics of the storage capacitor are discussed by comparing with those of a large area planar capacitor whose structure is the same as the storage capacitor     

Analytical model for high-performance shallow-junction-welltransistor (SJET) with a fully depleted channel structure

An analytical model for a very-shallow-junction-well transistor (SJET) is described. Solving the one-dimensional Poisson equation at the channel region, it was found that the channel depletion-layer charge can be reduced by extending the p-n junction depletion layer width between the well region and the substrate in the SJET. Therefore, in the SJET, the p-well thickness and the substrate bias are very important factors for realizing its high performance. According to this model, larger carrier mobility in the inversion layer and smaller subthreshold swing can be realized in the SJET compared to a conventional MOSFET. Moreover, by controlling the electron injection from the inversion layer to the substrate at high substrate bias, a vertical operating mode in the SJET (VSJET) can also be realized     

MOSFET-Like Behavior of a-InGaZnO Thin-Film Transistors With Plasma-Exposed Source–Drain Bulk Region

In this paper, we analyzed electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with plasma-exposed source–drain (S/D) bulk region. The parasitic resistance and effective channel length characteristics exhibit similar behavior with that of crystalline silicon metal oxide-semiconductor field effect transistor (c-Si MOSFET) that has doped S/D bulk region. The transfer curves little changed with gate overlap variation, and the width-normalized parasitic resistance obtained from transmission line method was as low as 3 to 6 $Omega cdot$ cm. The effective channel length was shorter than the mask channel length and showed gate-to-source $({rm V}_{rm GS})$ voltage dependency that is frequently observed for lightly doped drain (LDD) MOSFET. Experimental and simulation results showed that the plasma exposure caused an LDD-like doping effect in the S/D bulk region by inducing oxygen vacancy in the a-IGZO layer.      

Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET

For the first time, we report the combined application of a SiGe source and a delta-doped p⁺ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications     

Optimizing the match in weakly inverted MOSFET's by gated lateralbipolar action

The on-chip n-type MOSFET current mirror circuit with different drawn gate widths and lengths has been fabricated, and has been characterized across the wafer with back gate slightly forward biased. The weakly inverted MOSFET device with a small back-gate forward bias represents equivalently the high-gain gated lateral bipolar transistor in low-level injection. Experimental results have exhibited a substantial improvement in the match of the drain current in weak inversion due to action of the gated lateral bipolar transistor, especially for the small size devices. The extensively measured mismatch of the weak inversion drain current has been successfully reproduced by an analytic statistical model with back-gate forward bias and device size both as input parameters. The experimentally extracted variations in process parameters such as the flat-band voltage and the body effect coefficient each have been found to follow the inverse square root of the device area. The mismatch model thus can serve as a quantitative design tool, and has been used to optimize the trade-off between the device area and the match with the forward back-gate bias as a parameter     

A novel technique to determine the gate and drain bias dependentseries resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived     

On-line extraction of model parameters of a long buried-channel MOSFET

A buried-channel depletion MOS transistor has an implanted neutral conducting channel between the source and drain due to which the device works in a variety of modes such as accumulation, accumulation-depletion, depletion, inversion-depletion, inversion, etc., and presents a more complex structure than an enhancement-mode device. For precise circuit simulation, accurate and on-line extraction of model parameters has assumed significant importance. It is found that representing the implanted buried channel by an equivalent box with average doping and junction depth gives a convenient trade-off between simplicity in modeling and accuracy in device characterization. The present work proposes a method of deriving the necessary model parameters through the measurement of a single device parameter, namely drain conductance under different operating conditions. The on-line measurements carried on a boron-implanted relatively long buried-channel MOSFET have been used to predict the best box for the profile and give other model parameters necessary for circuit simulation. It is shown that the method is most insensitive to measurement conditions compared to other techniques.     

Ring Oscillator Technique for MOSFET $CV$ Characterization

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the $CV$ characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At $≪$1 MHz, the frequency divided output is compatible with standard in-line test. Data from experimental partially depleted silicon-on-insulator hardware at the 65-nm CMOS technology node are presented.      

A comprehensive analysis of IMD behavior in RF CMOS power amplifiers

This paper presents a comprehensive analysis of nonlinear intermodulation distortion (IMD) behavior in RF CMOS power amplifiers (PAs). Separate analyses are presented for small- and large-signal operation regimes. Especially, a new, simple, large-signal behavioral IMD analysis method is presented that allows the mechanisms dominant for IMD generation to be identified and their individual contributions to be studied. By combining these analyses, typical IMD versus input power characteristics of MOSFET PAs can be predicted and understood for different classes of operation. Various measurements made on a 950-MHz RF CMOS PA are used to demonstrate typical behavior and validate the proposed theory. Prediction of IMD using a standard CMOS transistor model is also evaluated and is shown to give good agreement with the measurements.     

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.