A 100-MHz 100-dB operational amplifier with multipath nested Millercompensation structure

A 100-MHz bipolar operational amplifier has a gain of 100 dB. The op amp owes its high unity-gain bandwidth and high gain to an all-n-p-n signal path and multipath nested Miller compensation (MNMC). The phase margin with a 100-pF load is 40° at 100 MHz and the amplifier settles in 60 ns to 0.1% on a 1-V step. For comparison, a similar op amp without the multipath technique has been realized. The unity-gain bandwidth of this nested Miller compensation (NMC) op amp is 60 MHz and the settling time is 70 ns. Theory and measurements confirm that the multipath technique almost doubles the bandwidth of nested Miller compensated amplifiers     

Operational amplifier with 1-V rail-to-rail multipath-driven outputstage

A bipolar operational amplifier (op amp) with a rail-to-rail multipath-driven output stage that operates at supply voltages down to 1 V is presented. The bandwidth of this output stage is as high as possible, viz, equal to that of one of the output transistors, loaded by the output capacitance. The output voltage can reach both supply rails within 100 mV and the output current is ±15 mA. The op amp is designed to be loaded by a 100-pF capacitor and the unity-gain bandwidth is 3.4 MHz at a 60° phase margin. The voltage gain is 117 dB and the CMRR is 100 dB. The frequency behavior of the multipath-driven (MPD) topology has an improved performance when compared to that of previously presented low-voltage output stages. A figure of merit F_M for low-voltage op amps has been defined as the bandwidth-power ratio     

High-gain gaas mesfet op amp

A gain enhancement technique for GaAs MESFET op amps is presented. It uses positive feedback to cancel the output conductance between the driver and active load transistors in a common-source amplifier configuration. An op amp using this technique was implemented in a 1-µm non-self-aligned GaAs MESFET process. The op amp exhibited a dc gain of 60 dB and a unity-gain frequency of 840 MHz.Please address all correspondence to C.A.T. Salama.     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output     

The CMOS gain-boosting technique

The gain-boosting technique improves accuracy of cascoded CMOS circuits without any speed penalty. This is achieved by increasing the effect of the cascode transistor by means of an additional gain-stage, thus increasing the output impedance of the subcircuit. Used in opamp design, this technique allows the combination of the high-frequency behavior of a single-stage opamp with the high DC-gain of a multistage design. Bode-plot measurements show a DC-gain of 90 dB and a unity-gain frequency of 116 MHz (16 pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding with a closed-loop bandwidth of 18 MHz (35 pF load) and a settling accuracy better than 0.03 percent. A more general use of this technique is presented in the form of a transistor-like building block: the Super-MOST. This compound circuit behaves as a normal MOS-transistor but has an intrinsic gain gm.ro of more than 90 dB. The building block is self-biasing and therefore very easy to design with. An opamp consisting of only 8 Super-MOST's and 4 normal MOST's has been measured showing results equivalent to the design mentioned above.     

5V单电源供电的低噪声宽带放大器

以单片机MSP430F449为控制核心,设计了一个5 V单电源供电的低噪声宽带放大器。采用单位增益稳定低噪声运放OPA820作为前级放大,高速运放THS3091作为末级放大,其中利用DC-DC变换器TPS61087将5 V电压转化为18 V从而为末级放大电路供电。此外,系统还采用12位高速A/D转换器ADS803实现了测量并数字显示放大器输出电压峰峰值的功能,测量误差小于5%。本系统最高电压增益达到43 dB,上限及下限截止频率达到15 MHz和20 Hz,在50Ω负载上,最大不失真输出电压峰峰值为4.2 V。系统的输出噪声小于200 mV。     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

一种0.8V衬底驱动轨对轨运算放大器设计

采用衬底驱动技术设计低压低功耗轨对轨运算放大器。输入级采用衬底驱动MOSFET,有效避开阈值电压限制,将电源电压降至0.8V,实现低压下轨对轨共模输入范围。增加衬底驱动冗余差分对及反折式共源共栅求和电路实现恒定跨导控制,消除共模电压对输入级跨导的影响,输出采用前馈式AB类输出级,以提高动态输出电压范围。基于标准0.18μmCMOS工艺仿真运放,测得输出范围0.4～782.5mV,功耗48.8μW,电源抑制比58dB,CMRR65dB,直流开环增益63.8dB,单位增益带宽2.4MHz,相位裕度68°。版图设计采用双阱交叉空铅技术,面积为97.8μm×127.6μm。     

一种用于红外焦平面读出电路的输出缓冲器

设计了一种应用于红外焦平面读出电路的输出缓冲器,其建立时间短、静态功耗低、线性度高,在77 K和300 K温度下均能正常工作.该输出缓冲器采用0.5 μm CMOS工艺,5.5 V单电源供电,负载为一个25 pF电容并联一个500 kΩ电阻.模拟结果表明,该输出缓冲器在室温(300 K)时,开环增益为54.2 dB,单位增益带宽20 MHz,建立精度为0.1%时,建立时间为45 ns,静态功耗仅为3.3 mW;77 K时,开环增益为63 dB,单位增益带宽123 MHz,建立精度为0.1%时,建立时间为20 ns,静态功耗仅为3.72 mW.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

A rail-to-rail, constant gain, buffered op-amp for real time videoapplications

Inspired by Hogervorst et al's current switch idea, a buffered output stage operational amplifier was designed, which has high frequency, high dc gain, and rail-to-rail constant transconductance (G _m). This operational amplifier is the output stage of an analog/digital system which implements a Gabor convolution for real-time dynamic image processing and it is designed to interface the external analog-to-digital converter (ADC) with a very heavy load. The op amp was fabricated by the MOSIS service in a 2-μm, n-well CMOS, double polysilicon, double metal technology. The fabricated circuit operates from a single 5 V power supply and dissipates 10 mW. The open loop-gain of the fabricated circuit, A_vol, was measured as 67.2 dB for a 163 Ω∥33 pF load. Other dc and ac characteristics were measured for a 50 Ω∥33 pF load. The unify gain-bandwidth (GBW) was measured to be 11.4 MHz, the rising slew rate (SR+) 20.4 V/μs, the falling slew rate (SR-) 18.8 V/μs, and the offset voltage (V_off) 1 mV. The output swings with an amplitude of 3.24 V between 0.88 V and 4.12 V, which matches the input signal specifications of the ADC. In addition to rail-to-rail output voltage swing, the opamp has a constant G_m over the whole common mode (CM) voltage range     

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-μm CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of ±2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies     

A high-swing 2-V CMOS operational amplifier with replica-amp gainenhancement

A general gain-enhancement technique for operational amplifiers using a replica amplifier is described. Unlike conventional techniques such as cascoding, which increases the gain by increasing the output resistance, the replica-amp technique increase the gain by matching the main and the replica amps. Among the advantages of the replica-amp technique are low supply, high swing, and effectiveness with resistive loads. This technique has been demonstrated in a 1.2-μm CMOS two-stage op amp. Operating from ±1-V supplies, the op amp has an effective open-loop dc gain of greater than 10 000, while maintaining a high swing of 100 mV from either supply rails. The gain-enhancement circuit is shown to have only a small effect on the settling time experimentally, analytically, and in SPICE simulation     

基于0.13μm CMOS工艺的快速稳定的高增益Telescopic放大器设计

提出了一个0.13μm CMOS工艺下的快速稳定的高增益Telescopic放大器的设计。该设计采用了增益提高技术,分析了这种技术的增益模型和频率响应模型。后仿真结果表明,该设计开环直流增益为98 dB,在4.5 ns的建立时间之内达到0.02%的稳定精度,而且没有超调的现象,其等效输入噪声小于4 nV/rtHz,在1.2 V供电下消耗电流2 mA。     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion     

A multistage amplifier technique with embedded frequencycompensation

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-μm n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/μs average slew rate with 40 pF load     

The design of fully differential CMOS operational amplifiers without extra common-mode feedback circuits

A new fully differential CMOS operational amplifier (op amp) without extra common-mode feedback (CMFB) circuit is proposed and analyzed. In this op amp, simple inversely connected current-mirror pairs are used as active loads. From the theoretical analysis, it is shown that the common-mode signal can be efficiently suppressed by the reduced effective common-mode resistance of the active load. The proposed op amp with 2 pF capacitance loadings has an open-loop unity-gain bandwidth of 63 MHz, a phase margin 47°, and a dc gain of 67 dB in 3.5µm p-well CMOS technology. The common-mode gain at a single output node can be as low as —38 dB without extra CMFB circuit. Experimental results have successfully confirmed the capability of the efficient common-mode rejection.This work was supported by the United Microelectronics Corporation (UMC), Republic of China, under Grant C80054.     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。