Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.     

Adaptive Pre‐/Post‐Filters for NRT‐Based Stereoscopic Video Coding

Non‐real‐time delivery of stereoscopic video has been considered as a service scenario for 3DTV to overcome the limited bandwidth in the terrestrial digital television system. A hybrid codec combining MPEG‐2 and H.264/AVC has been suggested for the compression of stereoscopic video for 3DTV. In this paper, we propose a stereoscopic video coding scheme using adaptive pre‐/post‐filters (APPF) to improve the quality of 3D video while retaining compatibility with legacy video coding standards. The APPF are applied adaptively to blocks of various sizes determined by the macroblock coding mode and reference frame index. Experiment results show that the proposed method achieves up to 24.86% bit rate savings relative to a hybrid codec of MPEG‐2 and H.264/AVC including the inter‐view prediction.     

Reconfigurable media coding: An overview

This paper provides an overview of the rationale of the Reconfigurable Media Coding framework developed by MPEG standardization committee to overcome the limits of traditional ways of providing decoder specifications. Such framework is an extension of the Reconfigurable Video coding framework now encompassing also 3D Graphics coding standard. The idea of this approach is to specify decoders using an actor dataflow based representation consisting of self-contained processing units (coding tools) connected altogether and communicating by explicitly exchanging data. Such representation provides a specification for which several properties of the algorithms interesting for codec implementations are explicitly exposed and can be used for exploring different implementation objectives.     

A generic,comprehensive and granular decoder complexity model for the H.264/AVC standard

With recent advances in computing and communication technologies, ubiquitous access to high quality multimedia content such as high definition video using smartphones, netbooks, or tablets is a fact of our daily life. However, power consumption is still a major concern for portable devices. One approach to address this concern is to control and optimize power consumption using a power model for each multimedia application, such as a video decoder. In this paper, a generic, comprehensive and granular decoder complexity model for the baseline profile of H.264/AVC decoder has been proposed. The modeling methodology was designed to ensure a platform and implementation independent complexity model. Simulation results indicate that the proposed model estimates decoder complexity with an average accuracy of 92.15% for a wide range of test sequences using both the JM reference software and the x264 software implementation of H.264/AVC, and 89.61% for a dedicated hardware implementation of the motion compensation module. It should be noted that in addition to power consumption control, the proposed model can be used for designing a receiver-aware H.264/AVC encoder, where the complexity constraints of the receiver side are taken into account during compression. To further evaluate the proposed model, a receiver-aware encoder has been designed and implemented. Our simulation results indicate that using the proposed model the designed receiver aware encoder performs similar to the original encoder, while still being able to satisfy the complexity constraints of various decoders.     

Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs

Dataflow languages enable describing signal processing applications in a platform independent fashion, which makes them attractive in today’s multiprocessing era. RVC-CAL is a dynamic dataflow language that enables describing complex data-dependent programs such as video decoders. To this date, design automation toolchains for RVC-CAL have enabled creating workstation software, dedicated hardware and embedded application specific multiprocessor implementations out of RVC-CAL programs. However, no solution has been presented for executing RVC-CAL applications on generic embedded multiprocessing platforms. This paper presents a dataflow-based multiprocessor communication model, an architecture prototype that uses it and an automated toolchain for instantiating such a platform and the software for it. The complexity of the platform increases linearly as the number of processors is increased. The experiments in this paper use several instances of the proposed platform, with different numbers of processors. An MPEG-4 video decoder is mapped to the platform and executed on it. Benchmarks are performed on an FPGA board.     

MPEG Reconfigurable Video Coding: From specification to a reconfigurable implementation

This paper demonstrates that it is possible to produce automatic, reconfigurable, and portable implementations of multimedia decoders onto platforms with the help of the MPEG Reconfigurable Video Coding (RVC) standard. MPEG RVC is a new formalism standardized by the MPEG consortium used to specify multimedia decoders. It produces visual representations of decoder reference software, with the help of graphs that connect several coding tools from MPEG standards. The approach developed in this paper draws on Dataflow Process Networks to produce a Minimal and Canonical Representation (MCR) of MPEG RVC specifications. The MCR makes it possible to form automatic and reconfigurable implementations of decoders which can match any actual platforms. The contribution is demonstrated on one case study where a generic decoder needs to process a multimedia content with the help of the RVC specification of the decoder required to process it. The overall approach is tested on two decoders from MPEG, namely MPEG-4 part 2 Simple Profile and MPEG-4 part 10 Constrained Baseline Profile. The results validate the following benefits on the MCR of decoders: compact representation, low overhead induced by its compilation, reconfiguration and multi-core abilities.     

Rate-distortion driven decoder-side bitplane mode decision for distributed video coding

Distributed video coding (DVC) features simple encoders but complex decoders, which lies in contrast to conventional video compression solutions such as H.264/AVC. This shift in complexity is realized by performing motion estimation at the decoder side instead of at the encoder, which brings a number of problems that need to be dealt with. One of these problems is that, while employing different coding modes yields significant coding gains in classical video compression systems, it is still difficult to fully exploit this in DVC without increasing the complexity at the encoder side. Therefore, in this paper, instead of using an encoder-side approach, techniques for decoder-side mode decision are proposed. A rate-distortion model is derived that takes into account the position of the side information in the quantization bin. This model is then used to perform mode decision at the coefficient level and bitplane level. Average rate gains of 13–28% over the state-of-the-art DISCOVER codec are reported, for a GOP of size four, for several test sequences.     

Combining visual MPEG tools in the context of video adaptability

This paper proposes an interworking between MPEG-2 Intraframe coding and JPEG2000 international standards. The latter codec is integrated into the base layer of spatial scalability encoders whilst retaining full compatibility with MPEG-2 decoders. The proposed solution combines existing ISO/IEC MPEG standards and is elaborated upon with respect to three application areas; bitstream format portability and adaptability, bitstream switching and combined video scalability. The paper elaborates upon the proposed coding architectures and compatibility with published MPEG standards. The proposed coding architecture is compared against counterpart video transcoders, scalable and single layer codecs. It is shown that the proposed spatial encoder is superior to all the aforementioned codecs whilst enjoying an extensible architecture capable of serving restricted end systems and hosting additional scalable layers such as SNR and temporal scalabilities.     

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology.     

Sub-pixel motion estimation using kernel methods

Modern video codecs such as MPEG2, MPEG4-ASP and H.264 depend on sub-pixel motion estimation to optimise rate-distortion efficiency. Sub-pixel motion estimation is implemented within these standards using interpolated values at 1/2 or 1/4 pixel accuracy. By using these interpolated values, the residual energy for each predicted macroblock is reduced. However this leads to a significant increase in complexity at the encoder, especially for H.264, where the cost of an exhaustive set of macroblock segmentations needs to be estimated for optimal mode selection. This paper presents a novel scheme for sub-pixel motion estimation based on the whole-pixel SAD distribution. Both half-pixel and quarter-pixel searches are guided by a model-free estimation of the SAD surface using a two dimensional kernel method. While giving an equivalent rate distortion performance, this approach approximately halves the number of quarter-pixel search positions giving an overall speed up of approximately 10% compared to the EPZS quarter-pixel method (the state of the art H.264 optimised sub-pixel motion estimator).     

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and controllines without storage.     

一种H.264运动估计器的VLSI设计

MPEG4AVC／ITU—T H．264视频编码标准中所采用的多模式运动估计算法与传统的MPEG4、H．263 高级预测模式相比较而言，编码效率和性能都大大提高。但其诸如模式决策等问题却给运动估计器，特别是硬件运动估计器带来非常大的运算复杂度。本文提出一种H．264运动估计器硬件结构，它采用了新的模式决策算法和快速运动估计算法。仿真结果证明，这两种算法不但能使运动估计器降低其硬件实现成本，而且能减少模式决策和运动估计的时间。     

Audio decoding with frequency and complexity scalability

The paper describes a technique to design a complexity-scalable audio codec based on the partial reconstruction of the spectrum of a signal. The technique can be applied to any subband coding system based on cosine-modulated filterbanks. In the decoder, only a part of the subband is reconstructed, achieving an output signal with a lower sampling rate. The new synthesis filterbank, with a reduced number of channels and low computational cost, must be suitably designed. Hence, a computational saving is traded for lower quality in the reconstructed signal. The technique can be used to design low-complexity decoders compatible with the MPEG audio standard, i.e. able to decode only a part of an MPEG bit stream. In this way, a single MPEG-coded audio can be decoded by different receivers, i.e. standard and low-complexity ones. The problem of having fixed bit rate streams for all the decoders is discussed.     

Optimized dynamic compilation of dataflow representations for multimedia applications

This paper proposes two optimization methods based on dataflow representations and dynamic compilation that enhance flexibility and performance of multimedia applications. These optimization methods are intended to be used in an adaptive decoding context, or, in other terms, where decoders have the ability to adapt their decoding processes according to a bitstream. This adaptation is made possible by coupling the decoding information to process a stream inside a coded stream. In this paper, we use dataflow representations from the upcoming MPEG Reconfigurable Media Coding (RMC) standard to supply the decoding information to adaptive decoders. The benefits claimed by MPEG RMC are a reuse of coding tools between different specifications of decoder and an execution scalability on different processing units with a single specification, which can target either hardware and/or software platforms. These benefits are not yet achievable in practice as these specifications are not used at the receiver side in MPEG RMC. We valid these benefits and propose two optimizations for the generation and the execution of dataflow models: the first optimization takes benefits of the reuse of coding tools to reduce the time to obtain—configure—enforceable decoders. The second provides an efficient, dynamic, and scalable execution according to the features of the execution platform. We show the practical impact of these two optimizations on two decoder representations compliant with the MPEG-4 part 2 Simple Profile standard and the MPEG-4 Advanced Video Coding standard. The results shows that configuration time can be reduced by 3 and the performance of decoders can be increased by 50 %.     

A 195 mW/152 mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG

In this paper, we present a low power multimedia SoC with fully programmable 3-D graphics, MPEG4 codec, H.264 decoder, and JPEG codec for mobile devices. The mobile unified shader in 3-D graphics engine provides fully programmable 3-D graphics pipeline with 35% area and 28% power reduction. Low power lighting engine which employs logarithmic number datapath and the specialized lighting instruction enable 9.1 Mvertices/s vertex fill rate, which is 2.5 times improvement compared with previous works including transformations and OpenGL lighting. The SoC consumes less than 152 mW for video applications and less than 195 mW for 3-D graphics applications. The mobile unified shader and merged JPEG/MPEG4 codec reduce the silicon area and the SoC consumes 6.4 mm $times$ 6.4 mm in 0.13 $mu{hbox {m}}$ CMOS logic process.      

多标准视频解码器运动补偿存储架构设计

设计了一种适用于多标准视频解码器的存储架构,采用并行多级流水线用以实现AVS,MPEG-2,H.264标准中不同模式的图像预测计算,缓存机制避免了频繁访问外部存储器SDRAM,提高了运动补偿计算性能,减少了计算周期。使用90 nm的CMOS工艺库,在135 MHz的工作频率下综合,电路规模为45 kgate(千门)左右,处理一宏块需要大约520个时钟周期,结果表明该设计满足高清视频处理的要求。     

Design of an MPEG-2 codec

We review the design of a single-chip MPEG-2 a/v codec, covering the design process from the MPEG specifications and system requirements to the final design. After a brief overview of MPEG-1 and MPEG-2 standards, we examine the system requirements using as an example a universal serial bus (USB)-based MPEG-2 real-time digital video recorder. Finally, we present in more detail the hardware and software architecture of a specific MPEG a/v codec     

3D graphics coding in a reconfigurable environment

The main objective of this paper is to introduce the concept of Reconfigurable Graphic Coding and its validation under the form of a Functional Units (FU) library. The heterogeneity of data for 3D graphics objects representation requires the adaptability of the compression schemas to various types of content. While such adaptation can be relatively easy to support in software implementations, the same is much more difficult to implement in hardware. Although compression schemas inherently share the same data processing chain, the components forming it may vary with respect to the number and type of components to encode, data range and correlation type. Based on the analysis of the state of the art on 3D graphics compression approaches, we propose a set of processing units. We show how this set can be configured/connected into a network, including hardware networks, to obtain reference decoders. Moreover, the network can be reconfigured at runtime, based on information that is provided with the encoded object. This modular concept of functional units, allows optimized management of computation (such as identification of parallelizable functions or functions that are suitable for acceleration) relative to the hardware architecture (CPU, GPU, FPGA, etc.). In the four decoders presented, at least half of the FUs are being reused at least once. The results were performed by generating and compiling C code from RVC-CAL code and comparing the results with the MPEG reference software implementation. The FUs described in this paper were standardized by MPEG as part of the ISO/IEC 23001-4.     

支持H．264高清编解码器的片上系统MG3500

MG3500SoC是支持H．264高清编解码器的片上系统,内部集成一个嵌入式ARM926处理器,支持高清H．264编解码、MPEG-2解码和JPEG编解码。介绍了MG3500SoC的主要性能特点、引脚排列、主要接口功能及在DVR上的应用,以及MG3500SoC及其周围器件的硬件设计,提出了在设计中应注意的问题。